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1. general description the lpc15xx are arm cortex-m3 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption. the arm cortex-m3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. the lpc15xx operate at cpu frequencies of up to 72 mhz. the arm cortex-m3 cpu incorporates a 3-stage pipeline and uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. the arm cortex-m3 cpu also includes an internal prefetch unit that supports speculative branching. the lpc15xx includes up to 256 kb of fl ash memory, 32 kb of rom, a 4 kb eeprom, and up to 36 kb of sram. the peripheral compliment includes one full-speed usb 2.0 device, two spi interfaces, three usarts, one fast-mode plus i 2 c-bus interface, one c_can module, pwm/timer subsystem with fo ur configurable, multi-purpose state configurable timers (sctimer/pwm) with inpu t pre-processing unit, a real-time clock module with indep endent power supply and a dedicated oscillator, two 12-channel/12-bit, 2 msamples/s adcs, one 12-bit, 500 ksamples/s dac, four voltage comparators with internal voltage reference, and a temperature sensor. a dma engine can service most peripherals. for additional documentation related to the lpc15xx parts, see section 17 ? references ? . 2. features and benefits ? system: ? arm cortex-m3 processor (version r2p1), running at frequencies of up to 72 mhz. ? arm cortex-m3 built-in nested vectored interrupt controller (nvic). ? system tick timer. ? serial wire debug (swd) with four breakpoints and two watchpoints. ? single-cycle mult iplier supported. ? memory protection unit (mpu) included. ? memory: ? up to 256 kb on-chip flash programming memory with 256 byte page write and erase. ? up to 36 kb sram. ? 4 kb eeprom. lpc15xx 32-bit arm cortex-m3 microcontrol ler; up to 256 kb flash and 36 kb sram; fs usb, ca n, rtc, spi, usart, i2c rev. 1 ? 19 february 2014 product data sheet
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 2 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? rom api support: ? boot loader with boot options from flash or external source via usart, c_can, or usb ? usb drivers ? adc drivers ? spi drivers ? usart drivers ? i2c drivers ? power profiles and power mode configurat ion with low-power mode configuration option ? dma drivers ? c_can drivers ? flash in-application programming (iap) and in-system programming (isp). ? digital peripherals: ? simple dma engine with 18 channels and 20 programmable input triggers. ? high-speed gpio interface with up to 76 general-purpose i/o (gpio) pins with configurable pull-up/pull-down resistors, open-drain mode, input inverter, and programmable digital glitch filter. ? gpio interrupt generation capability with boolean pattern-matching feature on eight external inputs. ? two gpio grouped port interrupts. ? switch matrix for flexible config uration of each i/o pin function. ? crc engine. ? quadrature encoder interface (qei). ? configurable pwm/timer/motor control subsystem: ? up to four 32-bit counter/timers or up to eight 16-bit counter/timers or combinations of 16-bit and 32-bit timers. ? up to 28 match outputs and 22 configurable capture inputs with input multiplexer. ? up to 28 pwm outputs total. ? dither engine for improved average resolution of pulse edges. ? four state configurable time rs (sctimers) for highly fl exible, event-driven timing and pwm applications. ? sct input pre-processor unit (sctipu) for processing timer inputs and immediate handling of abort situations. ? integrated with adc threshold compare interrupts, temperature sensor, and analog comparator outputs for motor control feedback using analog signals. ? special-application and simple timers: ? 24-bit, four-channel, multi-rate timer (mrt ) for repetitive interrupt generation at up to four programmable, fixed rates. ? repetitive interrupt timer for general purpose use. ? windowed watchdog timer (wwdt). ? high-resolution 32-bit real-time clock (rtc) with selectable 1 s or 1 ms time resolution running in the always-on power domain. rtc can be used for wake-up from all low power modes in cluding deep power-down.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 3 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? analog peripherals: ? two 12-bit adc with up to 12 input cha nnels per adc and with multiple internal and external trigger inputs and sample rates of up to 2 msamples/s. each adc supports two independent conversion sequences. adc conversion clock can be the system clock or an asynchronous clock derived from one of the three plls. ? one 12-bit dac. ? integrated temperature sensor and band gap internal reference voltage. ? four comparators with external and internal voltage references (acmp0 to 3). comparator outputs are internally connected to the sctimer/pwms and adcs and externally to pins. each comparator outp ut contains a programmable glitch filter. ? serial interfaces: ? three usart interfaces with dma, rs-485 support, autobaud, and with synchronous mode and 32 khz mode for wake-up from deep-sleep and power-down modes. the usarts share a fractional baud-rate generator. ? two spi controllers. ? one i 2 c-bus interface supporting fast mode and fast-mode plus with data rates of up to 1mbit/s and with multiple address recognition and monitor mode. ? one c_can controller. ? one usb 2.0 full-speed device controller with on-chip phy. ? clock generation: ? 12 mhz internal rc oscillator trimmed to 1 % accuracy for ? 25 ? c ? t amb ? +85 ? c that can optionally be used as a system clock. ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? watchdog oscillator with a fr equency range of 503 khz. ? 32 khz low-power rtc oscillator with 32 khz, 1 khz, and 1 hz outputs. ? system pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run fr om the system oscillator or the internal rc oscillator. ? two additional plls for generating the usb and sctimer/pwm clocks. ? clock output function with divi der that can reflec t the crystal oscillator, the main clock, the irc, or the watchdog oscillator. ? power control: ? integrated pmu (power management unit) to minimize power consumption. ? reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. ? apis provided for optimizing power consumption in active and sleep modes and for configuring deep-sleep, power-down, and deep power-down modes. ? wake-up from deep-sleep and power-down modes on activity on usb, usart, spi, and i2c peripherals. ? wake-up from sleep, deep-sleep, power-down, and deep power-down modes from the rtc alarm or wake-up interrupts. ? timer-controlled self wake-up from deep power-down mode using the rtc high-resolution/wake-up 1 khz timer. ? power-on reset (por). ? brownout detect bod). ? jtag boundary scan modes supported. ? unique device serial number for identification.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 4 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? single power supply 2.4 v to 3.6 v. ? temperature range ? 40 c to +105 c. ? available as lqfp100, lqfp64, and lqfp48 packages. 3. applications 4. ordering information ? motor control ? solar inverters ? motion drives ? home appliances ? digital power supplies ? building and factory automation ? industrial and medical table 1. ordering information type number package name description version lpc1549jbd100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc1549jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1549jbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1548jbd100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc1548jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1547jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1547jbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 LPC1519JBD100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc1519jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1518jbd100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 lpc1518jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1517jbd64 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1517jbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 5 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 4.1 ordering options table 2. ordering options for lpc15xx type number flash/ kb eeprom/ kb total sram/ kb usb usart i 2 c spi c_can sctimer/ pwm 12-bit adc0/1 channels dac gpio lpc1549jbd100 256 4 36 yes 3 1 2 1 4 12/12 1 76 lpc1549jbd64 256 4 36 yes 3 1 2 1 4 12/12 1 44 lpc1549jbd48 256 4 36 yes 3 1 2 1 4 9/7 1 30 lpc1548jbd100 128 4 20 yes 3 1 2 1 4 12/12 1 76 lpc1548jbd64 128 4 20 yes 3 1 2 1 4 12/12 1 44 lpc1547jbd64 64 4 12 yes 3 1 2 1 4 12/12 1 44 lpc1547jbd48 64 4 12 yes 3 1 2 1 4 9/7 1 30 LPC1519JBD100 256 4 36 no 3 1 2 1 4 12/12 1 78 lpc1519jbd64 256 4 36 no 3 1 2 1 4 12/12 1 46 lpc1518jbd100 128 4 20 no 3 1 2 1 4 12/12 1 78 lpc1518jbd64 128 4 20 no 3 1 2 1 4 12/12 1 46 lpc1517jbd64 64 4 12 no 3 1 2 1 4 12/12 1 46 lpc1517jbd48 64 4 12 no 3 1 2 1 4 9/7 1 32
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 6 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 5. marking the lpc15xx devices typically have the following top-side marking for lqfp100 packages: lpc15xxjxxx xxxxxx xx xxxyywwxxx the lpc15xx devices typically have the followi ng top-side marking for lqfp64 packages: lpc15xxj xxxxxx xx xxxyywwxxx the lpc15xx devices typically have the followi ng top-side marking for lqfp48 packages: lpc15xxj xxxxxx xxxyy wwxxx field ?yy? states the year the device was m anufactured. field ?ww? states the week the device was manufactured during that year. fig 1. lqfp64/100 package marking fig 2. lqfp48 package marking 1 n terminal 1 index area aaa-011231 aaa-011232 terminal 1 index area 1 n
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 7 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 6. block diagram grey-shaded blocks show peripherals that can provide hardware triggers for dm a transfers or have dma request lines. fig 3. lpc15xx block diagram arm cortex-m3 test/debug interface swd/etm systick nvic mpu processor core precision irc system pll watchdog oscillator usb pll sct pll frequency measurement system oscillator rtc oscillator clock generation sctipu 256/128/64 kb flash 32 kb rom 36/20/12 kb sram 4 kb eeprom 12-bit dac memory port0/1/2 gint0/1 pint/ pattern match sctimer0/ pwm sctimer1/ pwm sctimer2/ pwm sctimer3/ pwm hs gpio qei dma trigger acmp0/ temperature sensor acmp1 acmp2 acmp3 input mux sctimer/pwm/motor control subsystem spi0 usart0 spi1 usart1 fm+ i2c0 usart2 c_can fs usb/ phy input mux syscon iocon pmu crc flash ctrl eeprom ctrl system/memory control mrt rit wwdt rtc timers serial peripherals 12-bit adc0 trigger mux analog peripherals 12-bit adc1 trigger mux ahb multilayer matrix ahb/apb bridges input mux input mux dma pads lpc15xx n pads n swm aaa-010869
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 8 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 7. pinning information 7.1 pinning fig 4. lqfp48 pin configuration (with usb) lpc1547jbd48 lpc1549jbd48 37 pio0_22/i2c0_scl 24 pio0_16/adc1_9 38 pio0_23/i2c0_sda 23 pio0_15/adc1_8 39 v dd 22 pio0_14/adc1_7/ sct1_out5 40 v ss 21 pio0_13/adc1_6 41 v ss 20 v ss 42 v dd 19 pio0_12/dac_out 43 pio0_24/sct0_out6 18 pio0_11/adc1_3 44 pio0_25/acmp0_i4 17 v ssa 45 pio0_26/acmp0_i3/ sct3_out3 16 v dda 46 pio0_27/acmp_i1 15 pio0_10/adc1_2 47 pio0_28/acmp1_i3 14 vrefp_dac_vddcmp 48 pio0_29/acmp2_i3/ sct2_out4 13 pio0_18/ sct0_out5 1 pio0_0/adc0_10/ sct0_out3 36 usb_dm 2 pio0_1/adc0_7/ sct0_out4 35 usb_dp 3 pio0_2/adc0_6/ sct1_out3 34 reset/pio0_21 4 pio0_3/adc0_5/ sct1_out4 33 swdio/ pio0_20/sct1_out6/ tms 5 pio0_4/adc0_4 32 rtcxout 6 pio0_5/adc0_3 31 rtcxin 7 pio0_6/adc0_2/ sct2_out3 30 vbat 8 pio0_7/adc0_1 29 swclk/ pio0_19/tck 9 pio0_8/adc0_0/tdo 28 pio0_17/wakeup/trst 10 vrefp_adc 27 v dd 11 vrefn 26 xtalin 12 pio0_9/adc1_1/tdi 25 xtalout aaa-009352
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 9 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fig 5. lqfp48 pin configuration (without usb) lpc1517jbd48 37 pio0_22/i2c0_scl 24 pio0_16/adc1_9 38 pio0_23/i2c0_sda 23 pio0_15/adc1_8 39 v dd 22 pio0_14/adc1_7/ sct1_out5 40 v ss 21 pio0_13/adc1_6 41 v ss 20 v ss 42 v dd 19 pio0_12/dac_out 43 pio0_24/sct0_out6 18 pio0_11/adc1_3 44 pio0_25/acmp0_i4 17 v ssa 45 pio0_26/acmp0_i3/ sct3_out3 16 v dda 46 pio0_27/acmp_i1 15 pio0_10/adc1_2 47 pio0_28/acmp1_i3 14 vrefp_dac_vddcmp 48 pio0_29/acmp2_i3/ sct2_out4 13 pio0_18/ sct0_out5 1 pio0_0/adc0_10/ sct0_out3 36 pio2_13 2 pio0_1/adc0_7/ sct0_out4 35 pio2_12 3 pio0_2/adc0_6/ sct1_out3 34 reset/pio0_21 4 pio0_3/adc0_5/ sct1_out4 33 swdio/ pio0_20/sct1_out6/ tms 5 pio0_4/adc0_4 32 rtcxout 6 pio0_5/adc0_3 31 rtcxin 7 pio0_6/adc0_2/ sct2_out3 30 vbat 8 pio0_7/adc0_1 29 swclk/ pio0_19/tck 9 pio0_8/adc0_0/tdo 28 pio0_17/wakeup/trst 10 vrefp_adc 27 v dd 11 vrefn 26 xtalin 12 pio0_9/adc1_1/tdi 25 xtalout aaa-009354
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 10 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller see table 3 for the full pin name. fig 6. lqfp64 pin configuration (with usb) lpc1549jbd64 lpc1548jbd64 lpc1547jbd64 49 pio0_22 32 pio0_16 50 pio0_23 31 pio0_15 51 pio1_7 30 pio0_14 52 v dd 29 pio0_13 53 pio1_8 28 pio1_3 54 pio1_9 27 v ss 55 v ss 26 v ss 56 v ss 25 pio1_2 57 v dd 24 pio0_12 58 pio0_24 23 pio0_11 59 pio1_10 22 v dd 60 pio0_25 21 v ssa 61 pio0_26 20 v dda 62 pio0_27 19 pio0_10 63 pio0_28 18 vrefp_dac_vddcmp 64 pio0_29 17 pio0_18 1 pio0_30 48 usb_dm 2pio0_0 47 usb_dp 3 pio0_31 46 pio1_6 4pio1_0 45 reset/pio0_21 5pio0_1 44 swdio/ pio0_20 6pio0_2 43 rtcxout 7pio0_3 42 rtcxin 8pio0_4 41 vbat 9pio0_5 40 swclk/ pio0_19 10 pio0_6 39 pio0_17/wakeup 11 pio0_7 38 pio1_11 12 pio0_8 37 v dd 13 vrefp_adc 36 xtalin 14 vrefn 35 xtalout 15 pio1_1 34 pio1_5 16 pio0_9 33 pio1_4 aaa-009353
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 11 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fig 7. lqfp64 pin configuration (without usb) lpc1519jbd64 lpc1518jbd64 lpc1517jbd64 49 pio0_22 32 pio0_16 50 pio0_23 31 pio0_15 51 pio1_7 30 pio0_14 52 v dd 29 pio0_13 53 pio1_8 28 pio1_3 54 pio1_9 27 v ss 55 v ss 26 v ss 56 v ss 25 pio1_2 57 v dd 24 pio0_12 58 pio0_24 23 pio0_11 59 pio1_10 22 v dd 60 pio0_25 21 v ssa 61 pio0_26 20 v dda 62 pio0_27 19 pio0_10 63 pio0_28 18 vrefp_dac_vddcmp 64 pio0_29 17 pio0_18 1 pio0_30 48 pio2_13 2pio0_0 47 pio2_12 3 pio0_31 46 pio1_6 4pio1_0 45 reset/pio0_21 5pio0_1 44 swdio/ pio0_20 6pio0_2 43 rtcxout 7pio0_3 42 rtcxin 8pio0_4 41 vbat 9pio0_5 40 swclk/ pio0_19 10 pio0_6 39 pio0_17/wakeup 11 pio0_7 38 pio1_11 12 pio0_8 37 v dd 13 vrefp_adc 36 xtalin 14 vrefn 35 xtalout 15 pio1_1 34 pio1_5 16 pio0_9 33 pio1_4 aaa-009376 fig 8. lqfp100 pin configuration lpc1548jbd100 lpc1518jbd100 76 100 50 26 1 25 75 51 aaa-009351
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 12 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 7.2 pin description most pins are configurable for multiple functi ons, which can be analo g or digital. digital inputs can be connected to several peripherals at once, however only one digital output or one analog function can be assigned to any on pin. the pin?s connections to internal peripheral blocks are configured by the switch matrix (swm), the in put multiplexer (input mux), and the sct input pre-processor unit (sctipu). the switch matrix enables certain fixed-pin functions that can only reside on specific pins (see table 3 ) and assigns all other pin functions (movable functions) to any available pin (see table 4 ), so that the pinout can be op timized for a given application. the input mux provides many choices (pins and internal signals) for selecting the inputs of the sctimer/pwms and the frequency measure block. pins that are connected to the input mux are listed in ta b l e 5 . if a pin is selected in the inpu t mux, it is directly connected to the peripheral input without being routed through the switch matrix. independently of being selected in the input mux, the same pin can also be assigned by the switch matrix to another peripheral input. four pins can also be connected directly to t he sctipu and at the same time be inputs to the input mux and the switch matrix (see ta b l e 5 ). table 3. pin description wi th fixed-pin functions symbol lqfp48 lqfp64 lqfp100 reset state [1] type description pio0_0/adc0_10/ sct0_out3 122 [2] i; pu io pio0_0 ? general purpose port 0 input/output 0. a adc0_10 ? adc0 input 10. o sct0_out3 ? sctimer0/pwm output 3. pio0_1/adc0_7/ sct0_out4 256 [2] i; pu io pio0_1 ? general purpose port 0 input/output 1. a adc0_7 ? adc0 input 7. o sct0_out4 ? sctimer0/pwm output 4. pio0_2/adc0_6/ sct1_out3 368 [2] i; pu io pio0_2 ? general purpose port 0 input/output 2. adc0_6 ? adc0 input 6. o sct1_out3 ? sctimer1/pwm output 3. pio0_3/adc0_5/ sct1_out4 4710 [2] i; pu io pio0_3 ? general purpose port 0 input/output 3. a adc0_5 ? adc0 input 5. o sct1_out4 ? sctimer1/pwm output 4. pio0_4/adc0_4 5813 [2] i; pu io pio0_4 ? general purpose port 0 input/output 4. this is the isp_0 boot pin for the lqfp48 package. a adc0_4 ? adc0 input 4. pio0_5/adc0_3 6914 [2] i; pu io pio0_5 ? general purpose port 0 input/output 5. a adc0_3 ? adc0 input 3. pio0_6/adc0_2/ sct2_out3 71016 [2] i; pu io pio0_6 ? general purpose port 0 input/output 6. a adc0_2 ? adc0 input 2. o sct2_out3 ? sctimer2/pwm output 3. pio0_7/adc0_1 81117 [2] i; pu io pio0_7 ? general purpose port 0 input/output 7. a adc0_1 ? adc0 input 1.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 13 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio0_8/adc0_0/tdo 9 12 19 [2] i; pu io pio0_8 ? general purpose port 0 input/output 8. in boundary scan mode: tdo (test data out). a adc0_0 ? adc0 input 0. pio0_9/adc1_1/tdi 12 16 24 [2] i; pu io pio0_9 ? general purpose port 0 input/output 9. in boundary scan mode: tdi (test data in). a adc1_1 ? adc1 input 1. pio0_10/adc1_2 15 19 28 [2] i; pu io pio0_10 ? general purpose port 0 input/output 10. a adc1_2 ? adc1 input 2. pio0_11/adc1_3 18 23 33 [2] i; pu io pio0_11 ? general purpose port 0 input/output 11. on the lqfp64 package, this pin is assigned to can0_rd in isp c_can mode. a adc1_3 ? adc1 input 3. pio0_12/dac_out 19 24 35 [3] i; pu io pio0_12 ? general purpose port 0 i nput/output 12. if this pin is configured as a digital input, the input voltage level must not be higher than v dda . a dac_out ? dac analog output. pio0_13/adc1_6 21 29 43 [2] i; pu io pio0_13 ? general purpose port 0 input/output 13. on the lqfp64 package, this pin is assigned to u0_rxd in isp usart mode. on the lqfp48 package, this pin is assigned to can0_rd in isp c_can mode. a adc1_6 ? adc1 input 6. pio0_14/adc1_7/ sct1_out5 22 30 45 [2] i; pu io pio0_14 ? general purpose port 0 input/output 14. on the lqfp48 package, this pin is assigned to u0_rxd in isp usart mode. a adc1_7 ? adc1 input 7. o sct1_out5 ? sctimer1/pwm output 5. pio0_15/adc1_8 23 31 47 [2] i; pu io pio0_15 ? general purpose port 0 input/output 15. on the lqfp48 package, this pin is assigned to u0_txd in isp usart mode. a adc1_8 ? adc1 input 8. pio0_16/adc1_9 24 32 49 [2] i; pu io pio0_16 ? general purpose port 0 input/output 16. on the lqfp48 package, this is the isp_1 boot pin. a adc1_9 ? adc1 input 9. pio0_17/wakeup/ trst 28 39 61 [4] i; pu io pio0_17 ? general purpose port 0 input/output 17. in boundary scan mode: trst (test reset). this pin triggers a wake-up from deep power-down mode. for wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. pull this pin high externally while in deep power-down mode. pull this pin low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. table 3. pin description wi th fixed-pin functions symbol lqfp48 lqfp64 lqfp100 reset state [1] type description
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 14 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio0_18/ sct0_out5 13 17 26 [5] i; pu io pio0_18 ? general purpose port 0 input/output 18. on the lqfp64 package, this pin is assigned to u0_txd in isp usart mode. on the lqfp48 package, this pin is assigned to can0_td in isp c_can mode. o sct0_out5 ? sctimer0/pwm output 5. swclk/ pio0_19/tck 29 40 63 [5] i; pu i swclk ? serial wire clock. swclk is enabled by default on this pin. in boundary scan mode: tck (test clock). io pio0_19 ? general purpose port 0 input/output 19. swdio/ pio0_20/sct1_out6/ tms 33 44 69 [5] i; pu i/o swdio ? serial wire debug i/o. swdio is enabled by default on this pin. in boundary scan mode: tms (test mode select). i/o pio0_20 ? general purpose port 0 input/output 20. o sct1_out6 ? sctimer1/pwm output 6. reset /pio0_21 34 45 71 [6] i; pu i reset ? external reset input: a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. in deep power-down mode, this pin must be pulled high externally. the reset pin can be left unconnected or be used as a gpio or for any mo vable function if an external reset function is not needed and the deep power-down mode is not used. i/o pio0_21 ? general purpose port 0 input/output 21. pio0_22/i2c0_scl 37 49 78 [7] ia io pio0_22 ? general purpose port 0 input/output 22. i/o i2c0_scl ? i 2 c-bus clock input/out put. high-current sink if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_23/i2c0_sda 38 50 79 [7] ia io pio0_23 ? general purpose port 0 input/output 23. i/o i2c0_sda ? i 2 c-bus data input/output. high-current sink if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_24/sct0_out6 43 58 90 [8] i; pu io pio0_24 ? general purpose port 0 input/output 24. high-current output driver. o sct0_out6 ? sctimer0/pwm output 6. pio0_25/acmp0_i4 44 60 93 [2] i; pu io pio0_25 ? general purpose port 0 input/output 25. a acmp0_i4 ? analog comparator 0 input 4. pio0_26/acmp0_i3/ sct3_out3 45 61 95 [2] i; pu io pio0_26 ? general purpose port 0 input/output 26. a acmp0_i3 ? analog comparator 0 input 3. o sct3_out3 ? sctimer3/pwm output 3. pio0_27/acmp_i1 46 62 97 [2] i; pu io pio0_27 ? general purpose port 0 input/output 27. a acmp_i1 ? analog comparator common input 1. table 3. pin description wi th fixed-pin functions symbol lqfp48 lqfp64 lqfp100 reset state [1] type description
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 15 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio0_28/acmp1_i3 47 63 98 [2] i; pu io pio0_28 ? general purpose port 0 input/output 28. a acmp1_i3 ? analog comparator 1 input 3. pio0_29/acmp2_i3/ sct2_out4 48 64 100 [2] i; pu io pio0_29 ? general purpose port 0 input/output 29. a acmp2_i3 ? analog comparator 2 input 3. o sct2_out4 ? sctimer2/pwm output 4. pio0_30/adc0_11 -11 [2] i; pu io pio0_30 ? general purpose port 0 input/output 30. a adc0_11 ? adc0 input 11. pio0_31/adc0_9 -33 [2] i; pu io pio0_31 ? general purpose port 0 input/output 31. on the lqfp64 package, this pin is assigned to can0_td in isp c_can mode. a adc0_9 ? adc0 input 9. pio1_0/adc0_8 -45 [2] i; pu io pio1_0 ? general purpose port 1 input/output 0. a adc0_8 ? adc0 input 8. pio1_1/adc1_0 -1523 [2] i; pu io pio1_1 ? general purpose port 1 input/output 1. a adc1_0 ? adc1 input 0. pio1_2/adc1_4 -2536 [2] i; pu io pio1_2 ? general purpose port 1 input/output 2. a adc1_4 ? adc1 input 4. pio1_3/adc1_5 -2841 [2] i; pu io pio1_3 ? general purpose port 1 input/output 3. a adc1_5 ? adc1 input 5. pio1_4/adc1_10 -3351 [2] i; pu io pio1_4 ? general purpose port 1 input/output 4. a adc1_10 ? adc1 input 10. pio1_5/adc1_11 -3452 [2] i; pu io pio1_5 ? general purpose port 1 input/output 5. a adc1_11 ? adc1 input 11. pio1_6/acmp_i2 -4673 [2] i; pu io pio1_6 ? general purpose port 1 input/output 6. a acmp_i2 ? analog comparator common input 2. pio1_7/acmp3_i4 -5181 [2] i; pu io pio1_7 ? general purpose port 1 input/output 7. a acmp3_i4 ? analog comparator 3 input 4. pio1_8/acmp3_i3/ sct3_out4 -5384 [2] i; pu io pio1_8 ? general purpose port 1 input/output 8. a acmp3_i3 ? analog comparator 3 input 3. o sct3_out4 ? sctimer3/pwm output 4. pio1_9/acmp2_i4 -5485 [2] i; pu io pio1_9 ? general purpose port 1 input/output 9. on the lqfp64 package, this is the isp_0 boot pin. a acmp2_i4 ? analog comparator 2 input 4. pio1_10/acmp1_i4 -5991 [2] i; pu io pio1_10 ? general purpose port 1 input/output 10. a acmp1_i4 ? analog comparator 1 input 4. pio1_11 - 38 58 [5] i; pu io pio1_11 ? general purpose port 1 input/output 11. on the lqfp64 package, this is the isp_1 boot pin. pio1_12 - - 9 [5] i; pu io pio1_12 ? general purpose port 1 input/output 12. pio1_13 - - 11 [5] i; pu io pio1_13 ? general purpose port 1 input/output 13. table 3. pin description wi th fixed-pin functions symbol lqfp48 lqfp64 lqfp100 reset state [1] type description
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 16 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio1_14/sct0_out7 --12 [5] i; pu io pio1_14 ? general purpose port 1 input/output 14. o sct0_out7 ? sctimer0/pwm output 7. pio1_15 - - 15 [5] i; pu io pio1_15 ? general purpose port 1 input/output 15. pio1_16 - - 18 [5] i; pu io pio1_16 ? general purpose port 1 input/output 16. pio1_17/sct1_out7 --20 [5] i; pu io pio1_17 ? general purpose port 1 input/output 17. o sct1_out7 ? sctimer1/pwm output 7. pio1_18 - - 25 [5] i; pu io pio1_18 ? general purpose port 1 input/output 18. pio1_19 - - 29 [5] i; pu io pio1_19 ? general purpose port 1 input/output 19. pio1_20/sct2_out5 --34 [5] i; pu io pio1_20 ? general purpose port 1 input/output 20. o sct2_out5 ? sctimer2/pwm output 5. pio1_21 - - 37 [5] i; pu io pio1_21 ? general purpose port 1 input/output 21. pio1_22 - - 38 [5] i; pu io pio1_22 ? general purpose port 1 input/output 22. pio1_23 - - 42 [5] i; pu io pio1_23 ? general purpose port 1 input/output 23. pio1_24/sct3_out5 --44 [5] i; pu io pio1_24 ? general purpose port 1 input/output 24. o sct3_out5 ? sctimer3/pwm output 5. pio1_25 - - 46 [5] i; pu io pio1_25 ? general purpose port 1 input/output 25. pio1_26 - - 48 [5] i; pu io pio1_26 ? general purpose port 1 input/output 26. pio1_27 - - 50 [5] i; pu io pio1_27 ? general purpose port 1 input/output 27. pio1_28 - - 55 [5] i; pu io pio1_28 ? general purpose port 1 input/output 28. pio1_29 - - 56 [5] i; pu io pio1_29 ? general purpose port 1 input/output 29. pio1_30 - - 59 [5] i; pu io pio1_30 ? general purpose port 1 input/output 30. pio1_31 - - 60 [5] i; pu io pio1_31 ? general purpose port 1 input/output 31. pio2_0 - - 62 [5] i; pu io pio2_0 ? general purpose port 2 input/output 0. pio2_1 - - 64 [5] i; pu io pio2_1 ? general purpose port 2 input/output 1. pio2_2 - - 72 [5] i; pu io pio2_2 ? general purpose port 2 input/output 2. pio2_3 - - 76 [5] i; pu io pio2_3 ? general purpose port 2 input/output 3. pio2_4 - - 77 [5] i; pu io pio2_4 ? general purpose port 2 input/output 4. on the lqfp100 package, this is the isp_1 boot pin. pio2_5 - - 80 [5] i; pu io pio2_5 ? general purpose port 2 input/output 5. on the lqfp100 package, this is the isp_0 boot pin. pio2_6 - - 82 [5] i; pu io pio2_6 ? general purpose port 2 input/output 6. on the lqfp100 package, this pin is assigned to u0_txd in isp usart mode. pio2_7 - - 86 [5] i; pu io pio2_7 ? general purpose port 2 input/output 7. on the lqfp100 package, this pin is assigned to u0_rxd in isp usart mode. pio2_8 - - 92 [5] i; pu io pio2_8 ? general purpose port 2 input/output 8. on the lqfp100 package, this pin is assigned to can0_td in isp c_can mode. table 3. pin description wi th fixed-pin functions symbol lqfp48 lqfp64 lqfp100 reset state [1] type description
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 17 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller pio2_9 - - 94 [5] i; pu io pio2_9 ? general purpose port 2 input/output 9. on the lqfp100 package, this pin is assigned to can0_rd in isp c_can mode. pio2_10 - - 96 [5] i; pu io pio2_10 ? general purpose port 2 input/output 10. pio2_11 - - 99 [5] i; pu io pio2_11 ? general purpose port 2 input/output 11. pio2_12 35 47 74 [5] i; pu io pio2_12 ? general purpose port 2 input/output 12. on parts lpc1519/17/18 only. pio2_13 36 48 75 [5] i; pu io pio2_13 ? general purpose port 2 input/output 13. on parts lpc1519/17/18 only. usb_dp 35 47 74 [10] - io usb bidirectional d+ line. pad includes internal 33 ? series termination resistor. on parts lpc1549/48/47 only. usb_dm 36 48 75 [10] - io usb bidirectional d ? line. pad includes internal 33 ? series termination resistor. on parts lpc1549/48/47 only. rtcxin 31 42 66 [9] - rtc oscillator input. this input should be grounded if the rtc is not used. rtcxout 32 43 67 [9] - rtc oscillator output. xtalin 26 36 54 [9] - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 25 35 53 [9] - output from the oscillator amplifier. vbat 30 41 65 - battery supply voltage. if no battery is used, tie vbat to vdd or to ground. v dda 16 20 30 - analog supply voltage. v dd and the analog reference voltages vrefp_adc and vrefp_dac_vddcmp must not exceed the voltage level on v dda . v dda should typically be the same voltages as v dd but should be isolated to minimize noise and error. v dda should be tied to v dd if the adc is not used. v dd 39, 27, 42 22, 52, 37, 57 4, 32, 70, 83, 57, 89 - 3.3 v supply voltage (2.4 v to 3.6 v). the voltage level on v dd must be equal or lower than the analog supply voltage v dda . vrefp_dac_vddcmp 14 18 27 [9] - dac positive reference voltage and analog comparator reference voltage. the voltage level on vrefp_dac_vddcmp must be equal to or lower than the voltage applied to v dda . vrefn 11 14 22 - adc and dac negative voltage reference. if the adc is not used, tie vrefn to v ss . table 3. pin description wi th fixed-pin functions symbol lqfp48 lqfp64 lqfp100 reset state [1] type description
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 18 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled; ia = inactive, no pull-up/dow n enabled; f = floating; if the pins are not used, tie floating pi ns to ground or power to mi nimize power consumption. [2] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as analog input, digital sect ion of the pad is disabled and the pin is not 5 v tolerant. this pin includes a 10 ns on/off glitch filter. by default, the glitch filter is turned on. [3] this pin is not 5 v tolerant due to special analog functionalit y. when configured for a digita l function, this pin is 3 v to lerant and provides standard digital i/o functions with configurable internal pull- up and pull-down resistors and hysteresis. when configured for d ac_out, the digital section of the pin is disabl ed and this pin is a 3 v tolerant analog outpu t. this pin includes a 10 ns on/off glitc h filter. by default, the glitch filter is turned on. [4] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, and configurable hysteresis. this pin includes a 10 ns on/off glitch filter. by default, the glitch filter is turned on. this pin is powered in deep power-down mode and can wake up the part. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [6] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [7] i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. [8] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis; includes high-current output driver. [9] special analog pin. [10] pad provides usb functions. it is des igned in accordance with the usb specif ication, revision 2. 0 (full-speed and low-speed mode only). this pad is not 5 v tolerant. vrefp_adc 10 13 21 - adc positive reference voltage. the voltage level on vrefp_adc must be equal to or lower than the voltage applied to v dda . if the adc is not used, tie vrefp_adc to v dd . v ssa 17 21 31 - analog ground. v ssa should typically be the same voltage as v ss but should be isolated to minimize noise and error. v ssa should be tied to v ss if the adc is not used. v ss 41, 20, 40 56, 26, 27, 55 88, 7, 39, 40, 68, 87 - ground. table 3. pin description wi th fixed-pin functions symbol lqfp48 lqfp64 lqfp100 reset state [1] type description table 4. movable functions function name type description u0_txd o transmitter output for usart0. u0_rxd i receiver input for usart0. u0_rts o request to send output for usart0. u0_cts i clear to send input for usart0. u0_sclk i/o serial clock input/output for usart0 in synchronous mode. u1_txd o transmitter output for usart1. u1_rxd i receiver input for usart1. u1_rts o request to send output for usart1.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 19 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller u1_cts i clear to send input for usart1. u1_sclk i/o serial clock input/output for usart1 in synchronous mode. u2_txd o transmitter output for usart2. u2_rxd i receiver input for usart2. u2_sclk i/o serial clock input/output for usart1 in synchronous mode. spi0_sck i/o serial clock for spi0. spi0_mosi i/o master out slave in for spi0. spi0_miso i/o master in slave out for spi0. spi0_ssel0 i/o slave select 0 for spi0. spi0_ssel1 i/o slave select 1 for spi0. spi0_ssel2 i/o slave select 2 for spi0. spi0_ssel3 i/o slave select 3 for spi0. spi1_sck i/o serial clock for spi1. spi1_mosi i/o master out slave in for spi1. spi1_miso i/o master in slave out for spi1. spi1_ssel0 i/o slave select 0 for spi1. spi1_ssel1 i/o slave select 1 for spi1. can0_td o can0 transmit. can0_rd i can0 receive. usb_vbus i usb vbus. sct0_out0 o sctimer0/pwm output 0. sct0_out1 o sctimer0/pwm output 1. sct0_out2 o sctimer0/pwm output 2. sct1_out0 o sctimer1/pwm output 0. sct1_out1 o sctimer1/pwm output 1. sct1_out2 o sctimer1/pwm output 2. sct2_out0 o sctimer2/pwm output 0. sct2_out1 o sctimer2/pwm output 1. sct2_out2 o sctimer2/pwm output 2. sct3_out0 o sctimer3/pwm output 0. sct3_out1 o sctimer3/pwm output 1. sct3_out2 o sctimer3/pwm output 2. sct_abort0 i sct abort 0. sct_abort1 i sct abort 1. adc0_pintrig0 i adc0 external pin trigger input 0. adc0_pintrig1 i adc0 external pin trigger input 1. adc1_pintrig0 i adc1 external pin trigger input 0. adc1_pintrig1 i adc1 external pin trigger input 1. dac_pintrig i dac external pin trigger input. dac_shutoff i dac shut-off external input. acmp0_o o analog comparator 0 output. table 4. movable functions ?continued function name type description
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 20 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller acmp1_o o analog comparator 1 output. acmp2_o o analog comparator 2 output. acmp3_o o analog comparator 3 output. clkout o clock output. rosc o analog comparator ring oscillator output. rosc_reset i analog comparator ring oscillator reset. usb_ftoggle o usb frame toggle. do not assign this function to a pin until a usb device is connected and the first sof interrupt has been received by the device. qei_pha i qei phase a input. qei_phb i qei phase b input. qei_idx i qei index input. gpio_int_bmat o output of the pattern match engine. swo o serial wire output. table 5. pins connected to the input mux and sct ipu symbol lqfp48 lqfp64 lqfp100 description pio0_2/adc0_6/sct1_out3 3 6 8 sct0 input mux pio0_3/adc0_5/sct1_out4 4 7 10 sct0 input mux pio0_4/adc0_4 5 8 13 sct2 input mux pio0_5/adc0_3 6 9 14 freqmeas pio0_7/adc0_1 8 11 17 sct3 input mux pio0_14/adc1_7/sct1_out5 22 30 45 sctipu input sample_in_a0 pio0_15/adc1_8 23 31 47 sct1 input mux pio0_16/adc1_9 24 32 49 sct1 input mux pio0_17/wakeup/trst 28 39 61 sct0 input mux swclk/pio0_19/tck 29 40 63 freqmeas reset /pio0_21 34 45 71 sct1 input mux pio0_25/acmp0_i4 44 60 93 sctipu input sample_in_a1 pio0_27/acmp_i1 46 62 97 sct2 input mux pio0_30/adc0_11 - 1 1 freqmeas sct0 input mux pio0_31/adc0_9 - 3 3 sct1 input mux pio1_4/adc1_10 - 33 51 sct1 input mux pio1_5/adc1_11 - 34 52 sct1 input mux pio1_6/acmp_i2 - 46 73 sct0 input mux pio1_7/acmp3_i4 - 51 81 sct0 input mux pio1_11 - 38 58 sct3 input mux sctipu input sample_in_a2 table 4. movable functions ?continued function name type description
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 21 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8. functional description 8.1 arm cortex-m3 processor the arm cortex-m3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumptio n. the arm cortex-m3 offers many new features, including a thumb-2 instruction set, low interrupt latency, hardware division, hardware single-cycle multip ly, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm cortex-m3 processor is described in detail in the cortex-m3 technical reference manual , which is available on the official arm website. 8.2 memory protection unit (mpu) the lpc15xx have a memory protection unit (mpu) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. the mpu allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses th at could potentially break the system. the mpu separates the memory into distinct regions and implements protection by preventing disallowed accesses. the mpu supports up to eight regions each of which can be divided into eight subregions. accesses to memory locations that are not defined in the mpu regions, or not permitted by the region setting, will cause the memo ry management fault exception to take place. pio1_12 - - 9 sct0 input mux pio1_13 - - 11 sct0 input mux pio1_15 - - 12 sct1 input mux pio1_16 - - 18 sct1 input mux pio1_18 - - 25 sct2 input mux pio1_19 - - 29 sct2 input mux pio1_21 - - 37 sct3 input mux pio1_22 - - 38 sct3 input mux pio1_26 - - 48 sctipu input sample_in_a3 pio1_27 - - 50 freqmeas table 5. pins connected to the input mux and sct ipu symbol lqfp48 lqfp64 lqfp100 description
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 22 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.3 on-chip flash programming memory the lpc15xx contain up to 256 kb on-chip flash program memory. the flash can be programmed using in-system programming (isp) or in-application programming (iap) via the on-chip boot loader software. flash updates via usb are supported as well. the flash memory is divided into 4 kb sector s with each sector consisting of 16 pages. individual pages of 256 byte each can be erased using the iap erase page command. 8.3.1 isp pin configuration the lpc15xx supports isp via the usart0, c_ can, or usb interfaces. the isp mode is determined by the state of two pins (isp_0 and isp_1) at boot time: the isp pin assignment is different for each package, so that the fewest functions possible are blocked. no more than four pins must be set aside for entering isp in any isp mode. the boot code assigns two isp pi ns for each package, which are probed when the part boots to determine whether or not to enter isp mode. on ce the isp mode has been determined, the boot loader configures the necessary serial pins for each package. pins which are not configured by the boot loader for the selected boot mode (for example can0_rd and can0_td in usart mode) can be assigned to any function through the switch matrix. 8.4 eeprom the lpc15xx contain 4 kb of on-chip by te-erasable and byte -programmable eeprom data memory. the eeprom can be programmed using in-application programming (iap) via the on-chip boot loader software. table 6. isp modes boot mode isp_0 isp_1 description no isp high high isp bypassed. part attempts to boot from flash. if the user code in flash is not valid, then enters isp via usb. c_can high low part enters isp via c_can. usb low high part enters isp via usb. usart0 low low part enters isp via usart0. table 7. pin assignments for isp modes boot pin lqfp48 lqfp64 lqfp100 isp_0 pio0_4 pio1_9 pio2_5 isp_1 pio0_16 pio1_11 pio2_4 usart mode u0_txd pio0_15 pio0_18 pio2_6 u0_rxd pio0_14 pio0_13 pio2_7 c_can mode can0_td pio0_18 pio0_31 pio2_8 can0_rd pio0_13 pio0_11 pio2_9 usb mode usb_vbus (same as isp_1) pio0_16 pio1_11 pio2_4
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 23 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.5 sram the lpc15xx contain a total 36 kb, 20 kb or 12 kb of contiguous, on-chip static ram memory. for each sram configur ation, the sram is divided in to three blocks: 2 x 16 kb + 4 kb for 36 kb sram, 2 x 8 kb + 4 kb for 20 kb sram, and 2 x 4 kb + 4 kb for 12 kb sram. the bottom 16 kb, 8 kb, or 4 kb are enabled by the bootloader and cannot be disabled. the next two sram blocks in each configuration can be disabled or enabled individually in the syscon block to save power. 8.6 on-chip rom the on-chip rom contains the boot loader and the following application programming interfaces (apis): ? in-system programming (isp) and in-application programming (iap) support for flash including iap erase page command. ? iap support for eeprom. ? flash updates via usb and c_can supported. ? usb api (hid, cdc, and msc drivers). ? dma, i2c, usart, spi , and c_can drivers. ? power profiles for configuring po wer consumption and pll settings. ? power mode configuration for configuring deep-sleep, power-down, and deep power-down modes. ? adc drivers for analog-to-digital conversion and adc calibration. table 8. lpc15xx sram configurations sram0 sram1 sram2 lpc1549/19 (total sram = 36 kb) address range 0x0200 0000 to 0x0200 3fff 0x0200 4000 to 0x0200 7fff 0x0200 8000 to 0x0200 8fff size 16 kb 16 kb 4 kb control cannot be disabled disable/enable disable/enable default enabled enabled enabled lpc1548/18 (total sram = 20 kb) address range 0x0200 0000 to 0x0200 1fff 0x0200 2000 to 0x0200 3fff 0x0200 4000 to 0x0200 4fff size 8 kb 8 kb 4 kb control cannot be disabled disable/enable disable/enable default enabled enabled enabled lpc1547/17 (total sram = 12 kb) address range 0x0200 0000 to 0x0200 0fff 0x0200 1000 to 0x0200 1fff 0x0200 2000 to 0x0200 2fff size 4 kb 4 kb 4 kb control cannot be disabled disable/enable disable/enable default enabled enabled enabled
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 24 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.7 ahb multilayer matrix fig 9. ahb multilayer matrix arm cortex-m3 test/debug interface dma ahb-to-apb bridge0 ahb-to-apb bridge1 eeprom hs gpio slaves sram2 system bus i-code bus d-code bus masters flash rom ahb multilayer matrix = master-slave connection dac acmp wwdt adc0 rit i2c0 qei swm spi0 spi1 usart1 pmu syscon usart2 pint gint0 gint1 mrt adc1 usb sram0 sram1 sctimer0/pwm sctimer1/pwm sctimer2/pwm sctimer3/pwm crc input mux rtc sctipu flash ctrl iocon eeprom ctrl usart2 c_can aaa-010870
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 25 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.8 memory map see section 8.5 ? sram ? for sram configuration. fig 10. memory map 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 8000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 0000 0x4005 8000 0x4005 c000 0x4008 0000 0x4008 0000 0x4001 c000 0x4001 4000 0x4000 0000 0x4002 c000 0x4003 0000 reserved 256 kb flash 0x0000 0000 0 gb 4 gb 0x0200 0000 0x0300 8000 0x0320 0000 0x0320 1000 0x1c01 0000 0x1c01 4000 0xffff ffff 4 kb eeprom reserved reserved 0x1000 0000 0x1c00 0000 apb peripherals 0 0x1c01 8000 0x1c01 c000 0x1c00 4000 crc gpio 0x1c00 8000 0x1c00 c000 dma 0x1c02 4000 0x4000 0000 0x4008 0000 apb peripherals 1 0x400f 0000 0x0200 9000 36 kb sram (lpc1549/19) 0x0200 5000 20 kb sram (lpc1548/18) 0x0200 3000 12 kb sram (lpc1547/17) reserved lpc15xx 0x0004 0000 32 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors reserved 0x0300 0000 reserved reserved reserved reserved reserved sctimer0/pwm 0x1c02 0000 sctimer1/pwm sctimer2/pwm 0x1c02 8000 sctimer3/pwm 0x4005 4000 0x4007 4000 0xe000 0000 0xe010 0000 private peripheral bus 0x4007 8000 adc0 dac analog comparators acmp reserved reserved rtc wwdt reserved usart0 qei reserved usart1 spi0 reserved i2c0 syscon input mux reserved switch matrix swm pmu spi1 reserved 0 1 2 4:3 5 6 9:7 16 15 14 17 18 19 22 20 21 28:23 29 10 11 13:12 31:30 apb peripherals 0x4008 4000 0x400a 0000 0x400a 4000 0x400a c000 0x400b 4000 0x400c 0000 0x400c 4000 0x400e 8000 0x400e c000 0x400f 0000 0x400f 4000 0x400f 8000 0x400f 0000 0x400b 0000 0x400a 8000 0x400b 8000 0x400b c000 0x400f c000 adc1 reserved mrt reserved rit sctipu flash ctrl fmc reserved pint reserved c_can iocon gint0 gint1 usart2 reserved reserved eeprom ctrl 0 7:1 8 9 10 11 12 26 25:17 16 27 28 29 30 31 13 14 15 usb aaa-010871
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 26 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.9 nested vectored interrupt controller (nvic) the nested vectored interrupt controller (nvi c) is part of the cortex-m3. the tight coupling to the cpu allows for lo w interrupt latency and efficient processing of late arriving interrupts. 8.9.1 features ? nested vectored interrupt controller that is an integral part of the arm cortex-m3. ? tightly coupled interrupt controller provides low interrupt latency. ? controls system exceptions and peripheral interrupts. ? the nvic supports 47 vectored interrupts. ? eight programmable interrupt priority leve ls with hardware pr iority level masking. ? software interrupt generation using the arm exceptions svcall and pendsv. ? support for nmi. ? arm cortex-m3 vector table offs et register vtor implemented. 8.9.2 interrupt sources typically, each peripheral device has one interrupt line connected to the nvic but can have several interrupt flags. individual interrupt flags can also represent more than one interrupt source. 8.10 iocon block the iocon block configures the electrical properties of the pins such as pull-up and pull-down resistors, h ysteresis, open-drain modes and input filters. remark: the pin function and whether the pin op erates in digital or analog mode are entirely under the control of the switch matrix. enabling an analog function through the switch matrix disables the digital pad. however, the internal pull-up and pull-down resistors as well as the pin hysteresis must be disabled to obtain an accurate reading of the analog input. 8.10.1 features ? programmable pull-up, pull-down, or repeater mode. ? all pins (except pio0_22 and pio0_23) are pulled up to 3.3 v (v dd = 3.3 v) if their pull-up resistor is enabled. ? programmable pseudo open-drain mode. ? programmable (on/off) 10 ns glitch filter on 36 pins (pio0_0 to pio0_17, pio0_25 to pio0_31, pio1_0 to pio1_10). the glit ch filter is turned on by default. ? programmable hysteresis. ? programmable input inverter. ? digital filter with pr ogrammable filter constant on all pins. 8.10.2 standard i/o pad configuration figure 11 shows the possible pin modes for standard i/o pins with analog input function:
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 27 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? digital output driver with co nfigurable open-drain output ? digital input: weak pull-up resistor (pmos device) enabled/disabled ? digital input: weak pull-down resistor (nmos device) enabled/disabled ? digital input: repeater mode enabled/disabled ? digital input: input digital filter configurable on all pins ? digital input: input glitch filter enabled/disabled on select pins ? analog input 8.11 switch matrix (swm) the switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowin g to connect many functions like the usart, spi, sct, and i2c functions to any pin that is not power or ground. these functions are called movable functions and are listed in table 4 . functions that need specialized pads like th e adc or analog comparator inputs can be enabled or disabled through the switch matrix. these functions are called fixed-pin functions and cannot move to other pins. the fixed-pin functions are listed in ta b l e 3 . if a fixed-pin function is disabled, any other mov able function can be assigned to this pin. fig 11. standard i/o pin configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input pin configured as digital output driver pin configured as digital input pin configured as analog input programmable digital filter 10 ns glitch filter aaa-010776
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 28 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.12 fast general-purpo se parallel i/o (gpio) device pins that are not connected to a specific peripheral function through the switch matrix are controlled by the gp io registers. pins may be dy namically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc15xx use accelerated gpio functions. ? an entire port value can be written in one instruction. ? mask, set, and clear operations are supported for the entire port. 8.12.1 features ? bit level port registers allow a single instruction to set and clear any number of bits in one write operation. ? direction control of individual bits. 8.13 pin interrupt/pattern match engine (pint) the pin interrupt block configures up to eight pins from the digital pins on ports 1 and 2 for providing eight external interrupts connected to the nvic. the input mux block is used to select the pins. the pattern match engine can be used, in conjunction with software, to create complex state machines based on pin inputs. any digital pin on ports 0 and 1 can be configured through the syscon block as input to the pin interrupt or pattern match engine. the registers that control the pin interrupt or pattern match engine are located on the io+ bus for fast single-cycle access. 8.13.1 features ? pin interrupts ? up to eight pins can be selected from all digital pins on ports 0 and 1 as edge- or level-sensitive interrupt requests. each request creates a separate interrupt in the nvic. ? edge-sensitive interrupt pins can interrupt on rising or falling edges or both. ? level-sensitive interrupt pins can be high- or low-active. ? pin interrupts can wake up the part from sleep mode, deep-sleep mode, and power-down mode. ? pin interrupt pattern match engine ? up to 8 pins can be selected from all digita l pins on ports 0 and 1 to contribute to a boolean expression. the boolean expression consists of specified levels and/or transitions on various combinations of these pins. ? each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. ? any occurrence of a pattern match can be programmed to also generate an rxev notification to the arm cpu. ? the pattern match engine d oes not facilitate wake-up.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 29 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.14 gpio group interrupts (gint0/1) the gpio pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sens itive interrupts. for each port/pin connected to one of the two the gpio grouped interr upt blocks (gint0 and gint1), the gpio grouped interrupt registers determine which pins are enabled to generate interrupts and what the active polarities of each of those inputs are. the gpio grouped in terrupt registers also se lect whether the interrup t output will be level or edge triggered and whether it will be based on the or or th e and of all of the enabled inputs. when the designated pattern is detected on the selected input pins, the gpio grouped interrupt block generates an interrupt. if the part is in a power-savings mode, it first asynchronously wakes the part up prior to asserting the interrupt request. the interrupt request line can be cleared by writing a one to the interrupt status bit in the control register. 8.14.1 features ? two group interrupts are supported to reflect two distinct interrupt patterns. ? the inputs from any number of digital pins can be enabled to contribute to a combined group interrupt. ? the polarity of each input enabled for th e group interrupt can be configured high or low. ? enabled interrupts can be logically combined through an or or and operation. ? the grouped interrupts can wake up the pa rt from sleep, deep-sleep or power-down modes. 8.15 dma controller the dma controller can access all memori es and the usart, spi, i2c, and dac peripherals using dma requests. dma transfers can also be triggered by internal events like the adc interrupts, the sct dma request signals, or the analog comparator outputs. 8.15.1 features ? 18 channels with 14 channels connected to peripheral request inputs. ? dma operations can be triggered by on-chip events. each dma channel can select one trigger input from 24 sources through the input mux. ? priority is user selectable for each channel. ? continuous priority arbitration. ? address cache with four entries. ? efficient use of data bus. ? supports single transfers up to 1,024 words. ? address increment options allow packing and/or unpacking data.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 30 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.16 input multiplexing (input mux) the input mux allows to select from multiple external and internal sources for the sct inputs, dma trigger inputs, and the frequency measure block. the input mux is implemented as a register interface with one source selection register for each input. the input mux can for example connect sct outputs, the adc interrupts, or the comparator outputs to the sct inputs and thus enables the sct to use a large variety of events to control the timing operation. the adcs and analog comparators also support input multiplexing using source selection registers as part of their configuration registers. 8.17 usb interface remark: the usb interface is available on parts lpc1549/48/47 only. the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot-plugging and dynamic configuration of the de vices. all transactions are initiated by the host controller. the usb interface consists of a full-speed device controller with on-chip phy (physical layer) for device functions. remark: configure the part in default power mode with the power profiles before using the usb (see section 8.40.1 ). do not use the usb when the part runs in performance, efficiency, or low-power mode. 8.17.1 full-speed usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, and endpoint buffer memory. the serial interface engine decodes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. 8.17.1.1 features ? dedicated usb pll available. ? fully compliant with usb 2.0 specification (full speed) . ? supports 10 physical (5 logical) endpoints including one control endpoint. ? single and double buffering supported. ? each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. ? supports wake-up from deep-sleep mode and power-down mode on usb activity and remote wake-up. ? supports softconnect functionality through internal pull-up resistor. ? internal 33 ? series termination resistors on usb_dp and usb_dm lines eliminate the need for external series resistors. ? supports link power management (lpm).
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 31 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.18 usart0/1/2 remark: all usart functions are movable functions and are assigned to pins through the switch matrix. do not connect usart functions to the open-drain pins pio0_22 and pio0_23. interrupts generated by the usart peripherals can wake up the part from deep-sleep and power-down modes if the usart is in synchronous mode, the 32 khz mode is enabled, or the cts interrupt is enabled. 8.18.1 features ? maximum bit rates of 4.5 mbit/s in asynchronous mode, 15 mbit/s in synchronous mode master mode, and 18 mbit/s in synchronous slave mode. ? 7, 8, or 9 data bits and 1 or 2 stop bits. ? synchronous mode with master or slave operation. includes data phase selection and continuous clock option. ? multiprocessor/multidrop (9-bit) mode with software address compare. ? rs-485 transceiver output enable. ? autobaud mode for automatic baud rate detection ? parity generation and checking: odd, even, or none. ? software selectable oversampling from 5 to 16 clocks in asynchronous mode. ? one transmit and one receive data buffer. ? rts/cts for hardware signaling for automatic flow control. software flow control can be performed using delta cts detect, transmit disable control, and any gpio as an rts output. ? received data and status can optionally be read from a single register ? break generation and detection. ? receive data is 2 of 3 sample "voting". status flag set when one sample differs. ? built-in baud rate generator with auto-baud function. ? a fractional rate divider is shared among all usarts. ? interrupts available for receiver ready, tr ansmitter ready, receiver idle, change in receiver break detect, framing error, pari ty error, overrun, underrun, delta cts detect, and receiver sa mple noise detected. ? loopback mode for testing of data and flow control. ? in synchronous slave mode, wakes up the part from deep-sleep and power-down modes. ? special operating mode allows operation at up to 9600 baud using the 32 khz rtc oscillator as the uart clock. this mode can be used while the device is in deep-sleep or power-down mode and can wake-up the device when a character is received. ? usart transmit and receive function s work with the syst em dma controller. 8.19 spi0/1 all spi functions are movable functions and are assigned to pins through the switch matrix. do not connect spi functions to the open-drain pins pio0_22 and pio0_23.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 32 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.19.1 features ? maximum data rates of 17 mbit/s in mast er mode and slave mode for spi functions connected to all digital pins except pio0_22 and pio0_23. ? data transmits of 1 to 16 bits supported directly. larger frames supported by software. ? master and slave operation. ? data can be transmitted to a slave without the need to read incoming data. this can be useful while setting up an spi memory. ? control information can optionally be writ ten along with data. this allows very versatile operation, including ?any length? frames. ? up to four slave select input/outputs with selectable polarity and flexible usage. ? supports dma transfers: spin transmit and receive functions work with the system dma controller. remark: texas instruments ssi and national microwire modes are not supported. 8.20 i2c-bus interface the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. the i2c-bus functions are fixed-pin functions and must be enabled through the switch matrix on the open-drain pins pio0_22 and pio0_23. 8.20.1 features ? supports standard and fast mode with data rates of up to 400 kbit/s. ? supports fast-mode plus with bit rates up to 1 mbit/s. ? fail-safe operation: when the power to an i 2 c-bus device is switched off, the sda and scl pins connected to the i 2 c-bus are floating and do not disturb the bus. ? independent master, slave, and monitor functions. ? supports both multi-master and multi-master with slave functions. ? multiple i 2 c slave addresses supported in hardware. ? one slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple i 2 c bus addresses. ? 10-bit addressing supported with software assist. ? supports smbus. ? supported by on-chip rom api.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 33 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.21 c_can controller area network (can) is the definition of a high performance communication protocol for serial data communication. the c_ can controller is designed to provide a full implementation of the can protocol accordin g to the can specification version 2.0b. the c_can controller can build powerful local ne tworks with low-cost multiplex wiring by supporting distributed real -time control with a high level of reliability. the c_can functions are movable functions and are assigned to pins through the switch matrix. do not connect c_can functions to the open-drain pins pio0_22 and pio0_23. 8.21.1 features ? conforms to protocol version 2.0 parts a and b. ? supports bit rate of up to 1 mbit/s. ? supports 32 message objects. ? each message object has its own identifier mask. ? provides programmable fifo mode (concatenation of message objects). ? provides maskable interrupts. ? supports disabled automatic retransmission (dar) mode for time-triggered can applications. ? provides programmable loop-back mode for self-test operation. 8.22 pwm/timer/motor control subsystem the sctimer/pwms (state configurable timer/pulse width modulators) and the analog peripherals support multiple ways of interconnecting their inputs and outputs and of interfacing to the pins and the dma controller. using the highly flexible and programmable connection scheme makes it easy to config ure various subsystems for motor control and complex timing and tracking applications. specifically, the inputs to the scts and the trigger inputs of the adcs and dma are selected through the input mux which offers a choice of many possible sources for each input or trigger. sct outputs are assigned to pins through the switch matrix allowing for many pinout solutions. 8.22.1 sctimer/pwm subsystem the sctimer/pwms can be configured to build a pwm controller with multiple outputs by programming the match and matchreload registers to control the base frequency and the duty cycle of each sctimer/pwm output. more complex waveforms that span multiple counter cycles or change behavior across or within counter cycles can be generated using the state capabilit y built into the sctimer/pwms. combining the pwm functions with the analog functions, the pwm output can react to control signals like comparator outputs or the adc interrupts. the sct ipu adds emergency shut-down functions and pre-processing of controlling events. for an overview of the pwm subsystem, see figure 12 ? pwm-analog subsystem ? . for high-speed pwm functionality, use only outputs that are fixed-pin functions to minimize pin-to-pin differences in output skew. see also table 22 ? sct output dynamic characteristics ? . this reduces the number of pwm outputs to five for each large sct.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 34 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.22.2 timer controlled subsystem the timers, the analog components, and the dma can be configured to form a subsystem that can run independently of the main processor under the control of the scts and any events that are generated by the a/d converters, the comparators, the sct output themselves, or the external pins. a/d conversi ons can be triggered by the timer outputs, the comparator outputs or by events from external pins. data can be transferred from the adcs to memory using the dma controller, an d the dma transfers can be triggered by the adcs, the comparator outputs, or by the timer outputs. for an overview of the subsystem, see figure 13 ? subsystem with timers, switch matrix, dma, and analog components ? . fig 12. pwm-analog subsystem input mux switch matrix switch matrix temp sensor vdda divider voltage reference trigger adc0/adc1 analog in interrupts acmp0 acmp1 acmp2 acmp3 outputs sct ipu analog in timer0 match/ matchreload sct0 outputs timer1 match/ matchreload sct1 outputs timer2 match/ matchreload sct2 outputs timer3 match/ matchreload sct3 outputs 8 x pwm out 8 x pwm out 6 x pwm out 6 x pwm out sct0/1/2/3 digital signal from/to pins analog signal from/to pins digital signal internal analog signal internal analog peripheral digital peripheral threshold crossing aaa-010873 4
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 35 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.22.3 sctimer/pwm in the large configuration (sct0/1) remark: for applications that require exact timing of the sct outputs (for example pwm), assign the outputs only to fixed-pin fu nctions to ensure that the output skew is nearly the same for all outputs. 8.22.3.1 features the following feature list summarizes the configuration for the two large scts. each large sct has a companion small sct (see section 8.22.4 ) with fewer inputs and outputs and a reduced feature set. ? each sct supports: ? 16 match/capture registers ? 16 events ? 16 states ? match register 0 to 5 support a fractional component for the dither engine fig 13. subsystem with timers, switch matrix, dma, and analog components temp sensor vdda divider voltage reference acmp0 acmp1 acmp2 acmp3 timer0 (sct0) timer1 (sct1) timer2 (sct2) timer3 (sct3) input mux outputs outputs trigger adc0/adc1 dac sct ipu analog in input mux dma switch matrix switch matrix analog in interrupts nvic dac_shutoff digital signal from/to pins analog signal from/to pins digital signal internal analog signal internal analog peripheral digital peripheral threshold crossing aaa-010874 4
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 36 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? 8 inputs and 10 outputs ? dma support ? counter/timer features: ? configurable as two 16-bit counters or one 32-bit counter. ? counters clocked by system clock or selected input. ? configurable as up counters or up-down counters. ? configurable number of match and capture registers. up to 16 match and capture registers total. ? upon match create the following events: stop, halt, limit counter or change counter direction; toggle outputs; create an interrupt; change the state. ? counter value can be loaded into capture register triggered by match or input/output toggle. ? pwm features: ? counters can be used in conjunction with match registers to toggle outputs and create time-proportioned pwm signals. ? up to eight single-edge or dual-edge controlled pwm outputs with up to eight independent duty cycles when configured as 32-bit timers. ? event creation features: ? the following conditions define an event: a counter match condition, an input (or output) condition such as an rising or fa lling edge or level, a combination of match and/or input/output condition. ? events can only have an effect while the counter is running. ? selected events can limit, halt, start, or stop a counter or change its direction. ? events trigger state changes, output togg les, interrupts, and dma transactions. ? match register 0 can be used as an automatic limit. ? in bi-directional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? state control features: ? a state is defined by the set of events that are allowed to happen in the state. ? a state changes into another state as result of an event. ? each event can be assigned to one or more states. ? state variable allows sequencing across multiple counter cycles. ? dither engine. ? integrated with an input pre-processing unit (sctipu) to combine or delay input events. inputs and outputs on the sctimer0/pwm and sctimer1/pwm are configured as follows: ? 8 inputs ? 7 inputs. each input except input 7 can select one of 23 sources from an input multiplexer. ? one input connected directly to the sc t pll for a high-speed dedicated clock input.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 37 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? 10 outputs (some outputs are connected to multiple locations) ? three outputs connected to external pins through the switch matrix as movable functions. ? five outputs connected to external pins through the switch matrix as fixed-pin functions. ? two outputs connected to the sctipu to sample or latch input events. ? one output connected to the other large sct ? four outputs connected to one small sct ? two outputs connected to each adc trigger input 8.22.4 state-configurable timers in the small configuration (sct2/3) remark: for applications that require exact timing of the sct outputs (for example pwm), assign the outputs only to fixed-pin fu nctions to ensure that the output skew is nearly the same for all outputs. 8.22.4.1 features the following feature list summarizes the config uration for the two small scts. each small sct has a companion large sct (see section 8.22.3 ) with more inputs and outputs and a dither engine. ? each sct supports: ? 8 match/capture registers ? 10 events ? 10 states ? 3 inputs and 6 outputs ? dma support ? counter/timer features: ? configurable as two 16-bit counters or one 32-bit counter. ? counters clocked by bus clock or selected input. ? up counters or up-down counters. ? configurable number of match and capture registers. up to 16 match and capture registers total. ? upon match create the following events: in terrupt, stop, limit timer or change direction; toggle outputs; change state. ? counter value can be loaded into capture register triggered by match or input/output toggle. ? pwm features: ? counters can be used in conjunction with match registers to toggle outputs and create time-proportioned pwm signals. ? up to six single-edge or dual-edge controlled pwm outputs with independent duty cycles if configured as 32-bit timers. ? event creation features:
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 38 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? the following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state. ? selected events can limit, halt, start, or stop a counter. ? events control state changes, outputs, interrupts, and dma requests. ? match register 0 can be used as an automatic limit. ? in bi-directional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? state control features: ? a state is defined by events that can take place in the state while the counter is running. ? a state changes into another state as result of an event. ? each event can be assigned to one or more states. ? state variable allows sequencing across multiple counter cycles. ? integrated with an input pre-processing unit (sctipu) to combine or delay input events. inputs and outputs on the sctimer2/pwm and sctimer3/pwm are configured as follows: ? 3 inputs. each input selects one of 21 sources from a pin multiplexer. ? 6 outputs (some outputs are connected to multiple locations) ? three outputs connected to external pins through the switch matrix as movable functions. ? three outputs connected to external pins through the switch matrix as fixed-pin functions. ? two outputs connected to the sct ipu to sample or latch input events. ? four outputs connected to the accompanying large sct ? two outputs connected to each adc trigger input 8.22.5 sct input processing unit (sctipu) the sctipu allows to block or propagate signal s to inputs of the sct under the control of an sct output. using the sctipu in this way, allows signals to be blocked from entering the sct inputs for a certain amount of time, for example while they are known to be invalid. in addition, the sctipu can generate a common signal from several combined input sources that can be selected on all sct i nputs. such a mechanism can be useful to create an abort signal that stops all timers. 8.22.5.1 features the sctipu pre-processes inputs to the state-configurable timers (sct). ? four outputs created from a selection of inpu t transitions. each output can be used as abort input to the scts or for any other application which requires a collection of multiple sct inputs to trigger an identical sct response.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 39 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? four registers to indicate which specific input sources caused the abort input to the scts. ? four additional outputs which can be sample d at certain times and latched at others before being routed to sct inputs. ? nine abort inputs. any combination of the abort inputs can trigger the dedicated abort input of each sct. 8.23 quadrature encoder interface (qei) a quadrature encoder, also known as a 2-chan nel incremental encoder, converts angular displacement into two pulse signals. by mo nitoring both the number of pulses and the relative phase of the two signals, the user code can track the position, direction of rotation, and velocity. in addition, a third channel, or index signal, can be used to reset the position counter. the quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over ti me and determine direction of rotation. in addition, the qei can capture the velocity of the encoder wheel. 8.23.1 features ? tracks encoder position. ? increments/decrements depending on direction. ? programmable for 2 ? or 4 ? position counting. ? velocity capture using built-in timer. ? velocity compare function with ?less than? interrupt. ? uses 32-bit registers for position and velocity. ? three position-compare registers with interrupts. ? index counter for re volution counting. ? index compare register with interrupts. ? can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. ? digital filter with prog rammable delays for encoder input signals. ? can accept decoded signal inputs (clock and direction). 8.24 analog-to-digital converter (adc) the adc supports a resolution of 12 bit and fast conversion rates of up to 2 msamples/s. sequences of analog-to-digital conversions can be triggered by multiple sources. possible trigger sources are internal connections to other on-chip peripherals such as the sct and analog comparator outp uts, external pins, and the arm txev interrupt. the adc supports a variable clocking scheme with clocking synchronous to the system clock or independent, asynchronous clocking for high-speed conversions. the adc includes a hardware threshold compar e function with zero-crossing detection. the threshold crossing interrupt is connected in ternally to the sct inputs for tight timing control between the adc and the scts.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 40 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.24.1 features ? 12-bit successive approximatio n analog-to-digital converter. ? 12-bit conversion rate of 2 mhz. ? input multiplexing among 12 pins and up to 4 internal sources. ? internal sources are the temperature sensor voltage, internal reference voltage, core voltage regulator output, and vdda/2. ? two configurable conversion sequ ences with independent triggers. ? optional automatic high/low threshold comparison and zero-crossing detection. ? power-down mode and low-power operating mode. ? measurement range vrefn to vrefp (typically 3 v; not to exceed vdda voltage level). ? burst conversion mode for single or multiple inputs. ? synchronous or asynchronous operati on. asynchronous operation maximizes flexibility in choosing the ad c clock frequency, synchron ous mode minimizes trigger latency and can eliminate uncertainty and jitter in response to a trigger. 8.25 digital-to-ana log converter (dac) the dac supports a resolution of 12 bits. conv ersions can be triggered by an external pin input or an internal timer. the dac includes an optional automatic hardware shut-off feature which forces the dac output voltage to zero while a high level on the external dac_shut off pin is detected. 8.25.1 features ? 12-bit digital-to-analog converter. ? supports dma. ? internal timer or pin external trigger for staged, jitter-free dac conversion sequencing. ? automatic hardware shut-off triggered by an external pin. 8.26 analog comparator (acmp) the lpc15xx include four analog comparators with seven selectable inputs each for each positive or negative input channel. two analog inputs are common to all four comparators. internal voltage inputs include a voltage ladder reference with selectable voltage supply source, the temperature sensor or the internal voltage reference. the analog inputs to the comparators are fixed-pin functions and must be enabled through the switch matrix. the outputs of each analog comparator are internally connected to the adc trigger inputs and to the sct inputs, so that the result of a voltage comparison can trigger a timer operation or an analog-to-digital conversion.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 41 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.26.1 features ? seven selectable inputs. fully configurable on either the positive side or the negative input channel. ? 32-stage voltage ladder internal reference for selectable voltages on each comparator; configurable on either po sitive or negative comparator input. ? voltage ladder source voltage is selectable from an external pin or the 3.3 v analog voltage supply. ? 0.9 v internal band gap reference voltage selectable as either positive or negative input on each comparator. ? temperature sensor voltage selectable as either positive or negative input on each comparator. ? voltage ladder can be separa tely powered down for applic ations only requiring the comparator function. ? individual comparator outputs can be connected internally to the sct and adc trigger inputs or the external pins. ? separate interrupt for each comparator. ? pin filter included on each comparator output. ? three propagation delay values are programmable to optimize between speed and power consumption. ? relaxation oscillator circuitr y output for a 555 style time r operation usin g comparator blocks 0 and 1. 8.27 temperature sensor the temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a ctat voltage (complement to absolute temperature). the output voltage varies inversely with device temperature with an absolute accuracy of better than 5 ? c over the full temperature range ( ? 40 ? c to +105 ? c). the temperature sensor is only approximately linear with a slight curvature. the output voltage is measured over different ranges of temperatures and fi t with linear-least-square lines. after power-up, the temperature sensor output must be allowed to settle to its stable value before it can be used as an accurate adc input. for an accurate measurement of the temper ature sensor by the adc, the adc must be configured in single-channel burst mode. the last value of a nine-conversion (or more) burst provides an accurate result. 8.28 internal voltage reference the internal voltage reference is an accurate 0.9 v and is the output of a low voltage band gap circuit. a typical value at t amb = 25 ? c is 0.905 v. the internal voltage reference can be used in the following applications: ? when the supply voltage v dd is known accurately, the internal voltage reference can be used to reduce the offset error e o of the adc code output. the adc error correction then increases the accuracy of temperature sensor voltage output measurements.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 42 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? when the adc is accurately calibrated, the internal voltage reference can be used to measure the power supply voltage. this requires calibration by recording the adc code of the internal voltage reference at different power supply levels yielding a different adc code value for each supply voltage level. in a particular application, the internal voltage reference can be measured and the actual power supply voltage can be determined from the stored calibration values. the calibration values can be stored in the eeprom for easy access. after power-up, the internal voltage reference must be allowed to settle to its stable value before it can be used as an adc reference voltage input. for an accurate measurement of the internal voltage reference by the adc, the adc must be configured in single-channel burst mode. the last value of a nine-conversion (or more) burst provides an accurate result. 8.29 multi-rate timer (mrt) the multi-rate timer (mrt) provides a repetiti ve interrupt timer with four channels. each channel can be programmed with an independent time interval, and each channel operates independently fr om the other channels. 8.29.1 features ? 24-bit interrupt timer ? four channels independently counting down from individually set values ? repeat and one-shot interrupt modes 8.30 windowed watc hdog timer (wwdt) the watchdog timer resets the controller if soft ware fails to periodically service it within a programmable time window. 8.30.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the wwdt is clocked by the dedicated wa tchdog oscillator (w dosc) running at a fixed frequency.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 43 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.31 repetitive inte rrupt (ri) timer the repetitive interrupt timer provides a free-r unning 48-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. any bits of the timer/compare can be masked such that they do not contribute to the match detection. the repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.31.1 features ? 48-bit counter running from the main cloc k. counter can be free-running or can be reset when an rit interrupt is generated. ? 48-bit compare value. ? 48-bit compare mask. an interrupt is generated when the counter value equals the compare value, after masking. this allows for co mbinations not poss ible with a simple compare. 8.32 system tick timer the arm cortex-m3 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 8.33 real-time clock (rtc) the rtc resides in a separate, always-on voltage domain with battery back-up. the rtc uses an independent 32 khz oscillator, also located in the alwa ys-on voltage domain. 8.33.1 features ? 32-bit, 1 hz rtc counter and associated match register for alarm generation. ? separate 16-bit high-resolution/wake-up timer clocked at 1 khz for 1 ms resolution with a more that one minute maximum time-out period. ? rtc alarm and high-resolution/wake-up ti mer time-out each generate independent interrupt requests. either time-out can wake up the part from any of the low power modes, including deep power-down.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 44 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.34 clock generation fig 14. clock generation system oscillator watchdog oscillator irc system oscillator irc irc usb pll usbpllclksel (usb pll clock select) system clock divider sysahbclkctrln (ahb clock enable) cpu, system control, pmu memories, peripheral clocks systick peripheral clock divider arm core systick ioconclkdiv clock divider iocon digital glitch filter arm trace clock clock divider arm trace usart peripheral clock divider fractional rate generator usart[n:0] wwdt clkoutsela (clkout clock select a) usb 48 mhz clock divider usb watchdog oscillator irc system oscillator usbclksel (usb clock select) clkout pin clock divider clkout pin system clock system pll irc system oscillator watchdog oscillator mainclkselb (main clock select b) mainclksela (main clock select a) syspllclksel (system pll clock select) main clock irc system oscillator rtc oscillator n system oscillator irc sct pll sctpllclksel (sct pll clock select) sct async adc clock divider adc adcasyncclksel (clock select) 32 khz rtc oscillator 32 khz clkoutselb (clkout clock select b) aaa-010875
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 45 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.35 power domains the lpc15xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the rtc and the backup registers. the vbat pin supplies power only to the rtc domain. the rtc requires a minimum of power to operate, which can be supplied by an external battery. the device core power (v dd ) is used to operate the rtc whenever v dd is present. therefor e, there is no power drain from the rtc battery when v dd is and v dd >= vbat + 0.3 v. 8.36 integrated oscillators the lpc15xx include the follo wing independent oscillators: the system oscillator, the internal rc oscillator (irc), the watchdog oscillator, and the 32 khz rtc oscillator. each oscillator can be used for multiple purposes. following reset, the lpc15xx op erates from the internal rc oscillator until software switches to a different clock source. the ir c allows the system to operate without any external crystal and the bootloader co de to operate at a known frequency. see figure 14 for an overview of the lpc15xx clock generation. fig 15. power distribution real-time clock backup registers wake-up control regulator 32 khz oscillator always-on/rtc power domain main power domain rtcxin vbat vdd rtcxout vdd vss to memories, peripherals, oscillators, plls to core to i/o pads adc temp sense acmp dac internal voltage ref adc power domain vdda vssa lpc15xx ultra low-power regulator wakeup aaa-010876
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 46 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.36.1 internal rc oscillator the irc can be used as the clock that drives the system pll and then the cpu. in addition, the irc can be selected as input to various clock dividers and as the clock source for the usb pll and the sct pll (see figure 14 ). the nominal irc frequency is 12 mhz. upon power-up, any chip reset, or wake-up from deep power-down mode, the lpc15xx use the irc as the clock source. software can later switch to one of the other available clock sources. 8.36.2 system oscillator the system oscillator can be used as a stable and accurate clock source for the cpu, with or without using the pll. for usb applications, use the syst em oscillator to provide the clock source to usb pll. the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. the system oscillator has a wake -up time of approximately 500 s. 8.36.3 watchdog oscillator the low-power watchdog oscillato r can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pi n. the watchdog oscilla tor nominal frequency is fixed at 503 khz. the frequency spread over processing and temperature is ? 40 %. 8.36.4 rtc oscillator the low-power rtc osc illator provides a 1 hz clock and a 1 khz clock to the rtc and a 32 khz clock output that can be us ed to obtain the main clock (see figure 14 ).the 32 khz oscillator output can be observed on the clkout pin to allow trimmi ng the rtc oscillator without interference from a probe. 8.37 system pll, us b pll, and sct pll the lpc15xx contain a three identical plls for generating the system clock, the 48 mhz usb clock, and an asynchronous clock for th e adcs and scts. the system pll is used to create the main clock. the sct and u sb plls create dedicated clocks for the asynchronous adc, the asynchrono us sct clock input, and the usb. remark: the usb pll is available on parts lpc1549/48/47 only. the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz. to support this frequency range, an additional divider keeps the cco within its frequency range while the pll is providing the desired output frequency. the output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. the pll output frequency must be lower than 100 mhz. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset. software can enable the pll later. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 47 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.38 clock output the lpc15xx feature a clock output function that routes the internal oscillator outputs, the pll outputs, or the main clock an output pin where they can be observed directly. 8.39 wake-up process the lpc15xx begin operation by using the 12 mhz irc oscillato r as the clock source at power-up and when awakened from deep power-down mode. this mechanism allows chip operation to resume quickl y. if the application uses the system oscillator or the pll, software must enable these comp onents and wait for them to stabilize. only then can the system use the pll and system oscillator as a clock source. 8.40 power control the lpc15xx support various power control features. there are four special modes of processor power reduction: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. the cpu clock rate can also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this power cont rol mechanism allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip peripherals. this register allows fine-tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals ha ve their own clock divider which provides additional power control. 8.40.1 power profiles the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile. the power configuration routine configures the lpc15xx for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability. ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock and to easily set the configuration options for deep-sleep and power-down modes. remark: when using the usb, configure the lpc15xx in default mode. 8.40.2 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and can generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, by memory systems and related controllers, and by internal buses.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 48 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.40.3 deep-sleep mode in deep-sleep mode, the lpc15xx is in sleep-mo de and all peripheral clocks and all clock sources are off except for the irc. the irc output is disabled unless the irc is selected as input to the watchdog timer. in addition all analog blocks are shut down and the flash is in stand-by mode. in deep-sleep mode, the application can keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. the lpc15xx can wake up from deep-sleep mode via reset, selected gpio pins, a watchdog timer interrupt, an interrupt generating usb port activity, an rtc interrupt, or any interrupts that the usart, spi, or i2c interfaces can create in deep-sleep mode. the usart wake-up requires the 32 khz mode, the synchronous mode, or the cts interrupt to be set up. deep-sleep mode saves power and allows for short wake-up times. 8.40.4 power-down mode in power-down mode, the lpc15xx is in sleep-mode and all peripheral clocks and all clock sources are off except for watchdog os cillator if selected. in addition all analog blocks and the flash are shut down. in powe r-down mode, the application can keep the bod circuit running for bod protection. the lpc15xx can wake up from power-down mode via reset, selected gpio pins, a watchdog timer interrupt, an interrupt generating usb port activity, an rtc interrupt, or any interrupts that the usart, spi, or i2c interfaces can create in power-do wn mode. the usart wake-up requires the 32 khz mode, the synchronous mode, or the cts interrupt to be set up. power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 8.40.5 deep power-down mode in deep power-down mode, power is shut off to the entire chip except for the wakeup pin and the always-on rtc power-domain. the lpc15xx can wake up from deep power-down mode via the wakeup pin or a wake-up signal generated by the rtc interrupt. the lpc15xx can be blocked from entering deep power-down mode by setting a lock bit in the pmu block. blocking the deep power-down mode enables the application to keep the watchdog timer or the bod running at all times. if the wakeup pin is used in th e application, an ex ternal pull-up resist or is required on the wakeup pin to hold it high while the pa rt is in deep power-do wn mode. pulling the wakeup pin low wakes up the part from deep power-down mode. in addition, pull the reset pin high to prevent it from floating while in deep power-down mode.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 49 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.41 system control 8.41.1 reset reset has four sources on the lpc15xx: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the irc an d initializes the flash controller. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. in deep power-down mode, an external pull-up resistor is required on the reset pin. the reset pin is operational in active, sleep, deep-sleep, and power-down modes if the reset function is selected through the switch ma trix for pin pio0_21 (this is the default). a low-going pulse as short as 50 ns executes the reset and thereby wakes up the part to its active state. the reset pin is not functional in deep power-down mode and must be pulled high externally while the pa rt is in deep power-down mode. 8.41.2 brownout detection the lpc15xx includes brown-out detection (bod) with two levels for monitoring the voltage on the v dd pin. if this voltage falls below one of two selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable re gister in the nvic to cause a cpu in terrupt. alternatively, software can monitor the signal by reading a dedicated status register. two threshold levels can be selected to cause a forced reset of the chip. 8.41.3 code security (code read protection - crp) crp provides different levels of security in th e system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. programming a specific pattern in to a dedicated flash location invokes crp. iap commands are not affected by the crp. fig 16. reset pin configuration 9 66 uhvhw ddd 9 '' 9 '' 9 '' 5 sx (6' (6' qv5& */,7&+),/7(5 3,1
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 50 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller in addition, isp entry the external pins can be disabled without enabling crp. for details, see the lpc15xx user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 selected , fully disables any access to the chip via the swd pins and the isp. this mode ef fectively disables i sp override using isp pin as well. if necessary, the applicati on must provide a flash update mechanism using iap calls or using a call to the reinvoke isp command to enable flash update via the usart. in addition to the three crp levels, sampling of the isp pins for valid user code can be disabled. for details, see the lpc15xx user manual . caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 51 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 8.42 emulation and debugging debug functions are integrated into the arm co rtex-m3. serial wire debug functions are supported in addition to a standard jt ag boundary scan. the arm cortex-m3 is configured to support up to four breakpoints and two watch points. the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd debug port is disabled while the lpc15xx is in reset. to perform boundary scan testing, follow these steps: 1. erase any user code residing in flash. 2. power up the part with the reset pin pulled high externally. 3. wait for at least 250 ? s. 4. pull the reset pin low externally. 5. perform boundary scan operations. 6. once the boundary scan operations are completed, assert the trst pin to enable the swd debug mode, and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes. 9. limiting values table 9. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (3.3 v) [2] ? 0.5 v dda v v dda analog supply voltage ? 0.5 +4.6 v v ref reference voltage on pin vrefp_dac_vddcmp ? 0.5 v dda v on pin vrefp_adc ? 0.5 v dda v v bat battery supply voltage ? 0.5 +4.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(io) supply voltage is present [3] [4] ? 0.5 +5.5 v on i2c open-drain pins pio0_22, pio0_23 [5] ? 0.5 +5.5 v 3 v tolerant i/o pin without over-voltage protection. applies to pio0_12. [6] ? 0.5 v dda v usb_dm, usb_dp pins ? 0.5 v dd + 0.5 v v ia analog input voltage [7] [8] [9] ? 0.5 +4.6 v v i(xtal) crystal input voltage [2] ? 0.5 +2.5 v v i(rtcx) 32 khz oscillator input voltage [2] ? 0.5 +4.6 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 52 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] maximum/minimum voltage above the maximum operating voltage (see table 11 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] applies to all 5 v tolerant i/o pins except true open-drain pins pio0_22 and pio0_23 and except the 3 v tolerant pin pio0_12 . [4] including the voltage on outputs in 3-state mode. [5] v dd(io) present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd(io) is powered down. [6] applies to 3 v tolerant pins pio0_12. [7] an adc input voltage above 3.6 v can be applied for a short ti me without leading to immediate, unrecoverable failure. accumu lated exposure to elevated voltages at 4.6 v must be less than 10 6 s total over the lifetime of the device. applying an elevated voltage to the adc inputs for a long time affects the reliabili ty of the device and reduces its lifetime. [8] if the comparator is configured with the common mode input v ic = v dd , the other comparator input can be up to 0.2 v above or below v dd without affecting the hysteresis range of the comparator function. [9] it is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] dependent on package type. [11] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. 10. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. i latch i/o latch-up current ? (0.5v dd(io) ) < v i < (1.5v dd(io) ); t j < 125 ?c - 100 ma t stg storage temperature [10] ? 65 +150 ?c t j(max) maximum junction temperature - 150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [11] -5k v table 9. limiting values ?continued in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit t j t amb p d r th j a ? ?? ? ?? +=
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 53 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller table 10. thermal resistance value (c/w): 15 % symbol parameter conditions typ unit lqfp48 ? ja thermal resistance junction-to-ambient jedec (4.5 in ? 4 in) 0 m/s 64 ? c/w 1 m/s 55 ? c/w 2.5 m/s 50 ? c/w 8-layer (4.5 in ? 3 in) 0 m/s 96 ? c/w 1 m/s 76 ? c/w 2.5 m/s 67 ? c/w ? jc thermal resistance junction-to-case 13 ? c/w ? jb thermal resistance junction-to-board 16 ? c/w lqfp64 ? ja thermal resistance junction-to-ambient jedec (4.5 in ? 4 in) 0 m/s 51 ? c/w 1 m/s 45 ? c/w 2.5 m/s 41 ? c/w 8-layer (4.5 in ? 3 in) 0 m/s 75 ? c/w 1 m/s 60 ? c/w 2.5 m/s 54 ? c/w ? jc thermal resistance junction-to-case 13 ? c/w ? jb thermal resistance junction-to-board 17 ? c/w lqfp100 ? ja thermal resistance junction-to-ambient jedec (4.5 in ? 4 in) 0 m/s 42 ? c/w 1 m/s 37 ? c/w 2.5 m/s 34 ? c/w 8-layer (4.5 in ? 3 in) 0 m/s 59 ? c/w 1 m/s 4 8 ? c/w 2.5 m/s 44 ? c/w ? jc thermal resistance junction-to-case 12 ? c/w ? jb thermal resistance junction-to-board 17 ? c/w
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 54 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 11. static characteristics table 11. static characteristics t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) [2] 2.4 3.3 v dda v v dda analog supply voltage 2.4 3.3 3.6 v v ref reference voltage on pin vrefp_dac_vddcmp 2.4 - v dda v on pin vrefp_adc 2.7 - v dda v v bat battery supply voltage 2.4 3.3 3.6 v i dd supply current active mode; code while(1){} executed from flash; system clock = 12 mhz; default mode; v dd = 3.3 v [3] [4] [5] [7] [8] -4.3 -ma system clock = 12 mhz; low-current mode; v dd = 3.3 v [3] [4] [5] [7] [8] -2.7 -ma system clock = 72 mhz; default mode; v dd = 3.3 v [3] [4] [7] [8] [10] - 19.3 - ma system clock = 72 mhz; low-current mode; v dd = 3.3 v [3] [4] [7] [8] [10] -18 -ma sleep mode; system clock = 12 mhz; default mode; v dd = 3.3 v [3] [4] [5] [7] [8] -2.1 -ma system clock = 12 mhz; low-current mode; v dd = 3.3 v [3] [4] [5] [7] [8] -1.5 -ma system clock = 72 mhz; default mode; v dd = 3.3 v [3] [4] [10] [7] [8] -8.0 -ma system clock = 72 mhz; low-current mode; v dd = 3.3 v [3] [4] [10] [7] [8] -7.3 -ma i dd supply current deep-sleep mode; v dd = 3.3 v; t amb =25 ?c [3] [4] [11] - 310 380 ? a t amb =105 ?c - - 620 ? a i dd supply current power-down mode; v dd = 3.3 v t amb =25 ?c [3] [4] [11] - 3.8 8 ? a t amb =105 ?c - - 163 ? a i dd supply current deep power-down mode; v dd = 3.3 v; vbat = 0 or vbat = 3.0 v rtc oscillator running t amb =25 ?c [3] [12] [13] -1.1 1.3 [14] ? a t amb =105 ?c- - 1 5 ? a rtc oscillator input grounded; t amb =25 ?c [3] [12] - 560 - na
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 55 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller i bat battery supply current deep power-down mode; v dd = v dda = 3.3 v; vbat = 3.0 v [13] 0-n a v dd and v dda tied to ground; vbat = 3.0 v [13] 1- ? a standard port pins config ured as digital pins, reset ; see figure 17 i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.5 10 [14] na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.5 10 [14] na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.5 10 [14] na v i input voltage v dd ? 2.4 v; 5 v tolerant pins except pio0_12 [16] [18] 0- 5v v dd ? 2.4 v; on 3 v tolerant pin pio0_12 0- v dda v dd = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage 2.4 v <= v dd < 3.0 v 0.30 - - v 3.0 v <= v dd <= 3.6 v 0.35 - - v v oh high-level output voltage i oh =4 ma v dd ? 0.4 - - v v ol low-level output voltage i ol =4 ma - - 0.4 v i oh high-level output current v oh =v dd ? 0.4 v 4 - - ma i ol low-level output current v ol =0.4v 4 - - ma i ohs high-level short-circuit output current v oh =0v [19] -- -45ma i ols low-level short-circuit output current v ol =v dd [19] -- 50ma i pd pull-down current v i = 5 v 10 50 150 ? a i pu pull-up current v i =0v; ? 10 ? 50 ? 85 ? a v dd lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 56 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller v i input voltage v dd ? 2.4 v [16] [18] 0- 5.0v v dd = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage 2.4 v <= v dd < 3.0 v 0.30 - - v 3.0 v <= v dd <= 3.6 v 0.35 - - v v oh high-level output voltage i oh = 20 ma; 2.7 v <= v dd < 3.6 v v dd ? 0.4 - - v i oh = 12 ma; 2.4 v <= v dd < 2.7 v v dd ? 0.4 - - v v ol low-level output voltage i ol =4 ma - - 0.4 v i oh high-level output current v oh =v dd ? 0.4 v; 2.7 v <= v dd < 3.6 v 20 - - ma v oh =v dd ? 0.4 v; 2.4 v <= v dd < 2.7 v 12 - - ma i ol low-level output current v ol = 0.4 v 4 - - ma i ols low-level short-circuit output current v ol =v dd [19] -- 50ma i pd pull-down current v i =5v [20] 10 50 150 ? a i pu pull-up current v i =0v [20] ? 10 ? 50 ? 85 ? a v dd lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 57 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. [2] for usb operation: 3.0 v ??? v dd ? 3.6 v. [3] t amb =25 ? c. [4] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [5] irc enabled; system oscillator disabled; system pll disabled. [6] system oscillator enabled; i rc disabled; system pll disabled. [7] bod disabled. [8] all peripherals disabled in the sysahbclkctrl0/1 registers. pe ripheral clocks to usart, clko ut, and iocon disabled in system configuration block. [9] irc enabled; system oscillator disabled; system pll enabled. [10] irc disabled; system oscill ator enabled; system pll enabled. [11] all oscillators and analog blocks turned off: use api powe r_mode_configure() with mode parameter set to deep_sleep or power_down and peripheral parameter set to 0xff. [12] wakeup pin pulled high externally. v ih high-level input voltage 1.8 - - v v il low-level input voltage - - 1.0 v v hys hysteresis voltage 0.32 - - v z out output impedance 28 - 44 ? v oh high-level output voltage 2.9 - - v v ol low-level output voltage - - 0.18 v i oh high-level output current v oh =v dd ? 0.3 v [22] 4.8 - - ma i ol low-level output current v ol = 0.3 v [22] 5.0 - - ma i ols low-level short-circuit output current drive low; pad connected to ground - - 125 ma i ohs high-level short-circuit output current drive high; pad connected to ground - - 125 ma oscillator pins v i(xtal) crystal input voltage on pin xtalin ? 0.5 1.8 1.95 v v o(xtal) crystal output voltage on pin xtalout ? 0.5 1.8 1.95 v v i(rtcx) 32 khz oscillator input voltage on pin rtcxin [23] ? 0.5 - 3.6 v v o(rtcx) 32 khz oscillator output voltage on pin rtcxout [23] ? 0.5 - 3.6 v pin capacitance c io input/output capacitance pins with analog and digital functions [24] -- 7.1pf i 2 c-bus pins (pio0_22 and pio0_23) [24] - - 2.5 pf pins with digital functions only [24] -- 2.8pf table 11. static characteristics ?continued t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 58 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [13] rtc running or not running. [14] characterized on samples. not tested in production. [15] low-current mode pwr_low_current selected when runni ng the set_power routine in the power profiles. [16] including voltage on outputs in tri-state mode. [17] v dd supply voltage must be present. [18] tri-state outputs go into tri-state mode in deep power-down mode. [19] allowed as long as the current limit does not exceed the maximum current allowed by the device. [20] pull-up and pull-down currents are measured across t he weak internal pull-up/pull-down resistors. see figure 17 . [21] to v ss . [22] the parameter values specified are simulated and absolute values. [23] the input voltage of the rtc oscillator is limited as follows: v i(rtcx) , v o(rtcx) < max(vbat, v dd ). [24] including bonding pad capacitance. fig 17. pin input/output current measurement aaa-010819 + - pin pio0_n i oh i pu - + pin pio0_n i ol i pd v dd a a
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 59 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 11.1 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions: ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpio dir register. ? write 1 to the gpio clr register to drive the outputs low. conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl0/1 regist ers; all peripheral clocks disabled; internal pull-up resistors disabled; bo d disabled; low-current mode. 1 mhz - 6 mhz: irc enabled; pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz to 72 mhz: irc enabled; pll enabled. fig 18. active mode: typical supply current i dd versus supply voltage v dd aaa-011384 2.4 2.6 2.8 3 3.2 3.4 3.6 0 4 8 12 16 20 v dd (v) i dd dd i dd (ma) (ma) (ma) 12 mhz 24 mhz 48 mhz 60 mhz 72 mhz 36 mhz 6 mhz 1 mhz
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 60 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl0/1 regist ers; all peripheral clocks disabled; internal pull-up resistors disabled; bo d disabled; low-current mode. 1 mhz - 6 mhz: irc enabled; pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz to 72 mhz: irc enabled; pll enabled. fig 19. active mode: typical supply current i dd versus temperature conditions: v dd = 3.3 v; sleep mode entered from fl ash; all peripheral s disabled in the sysahbclkctrl0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled; bod disabled; low-current mode. 1 mhz - 6 mhz: irc enabled; pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz to 72 mhz: irc enabled; pll enabled. fig 20. sleep mode: typical supply current i dd versus temperature for different system clock frequencies aaa-011385 -40 -10 20 50 80 110 0 4 8 12 16 20 temperature (c) i dd dd i dd (ma) (ma) (ma) 12 mhz 24 mhz 48 mhz 60 mhz 72 mhz 36 mhz 6 mhz 1 mhz aaa-011386 -40 -10 20 50 80 110 0 2 4 6 8 temperature (c) i dd dd i dd (ma) (ma) (ma) 72 mhz 48 mhz 36 mhz 24 mhz 12 mhz 6 mhz 1 mhz 60 mhz
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 61 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: bod disabled; all oscillators and analog blocks disabled. use api power_mode_configure() with mode parameter set to deep_sleep and peripheral parameter set to 0xff. fig 21. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd conditions: bod disabled; all oscill ators and analog blocks disabled; v dd = 2.4 v to 3.6 v. use api power_mode_configure() with mode parameter se t to power_down and peripheral parameter set to 0xff. fig 22. power-down mode: typical supply current i dd versus temperature for different supply voltages v dd aaa-011234 -40 -10 20 50 80 110 280 300 320 340 360 380 400 temperature (c) i dd dd i dd (a) (a) (a) 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v aaa-011235 -40 -10 20 50 80 110 0 20 40 60 80 temperature (c) i dd dd i dd (a) (a) (a)
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 62 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller vbat = 0 v. fig 23. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd vbat = 3.3 v; v dd floating. fig 24. deep power-down mode: typical battery supply current i bat versus temperature aaa-011236 -40 -10 20 50 80 110 0 1 2 3 4 temperature (c) i dd dd i dd (a) (a) (a) 2.4 v 3.3 v 3.6 v aaa-011333 -40 -10 20 50 80 110 0 1 2 3 4 temperature (c) i bat bat i bat (a) (a) (a)
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 63 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 11.2 coremark data conditions: v dd = 3.3 v; active mode; all peripherals except one uart and the sct disabled in the sysahbclkctrl0/1 register; in ternal pull-up resistors enab led; bod disabled. measured with keil uvision v.4.73.0.0, c compiler v.5.03.0.76. fig 25. coremark score conditions: v dd = 3.3 v; t amb = 25 ? c; active mode; all peripherals except one uart and the sct disabled in the sysahbclkctrl0/1 registers; system clock derived from the irc; system oscillator disabled; internal pul l-up resistors enabled; bod disabled. measured with keil uvision v.4.73.0.0, c compiler v.5.03.0.76. fig 26. active mode: coremark power consumption i dd aaa-011746 0 12 24 36 48 60 72 2.35 2.4 2.45 2.5 2.55 2.6 2.65 system clock frequency (mhz) cm score cm score cm score efficiency cpu default/low current aaa-011747 0 12 24 36 48 60 72 0 5 10 15 20 25 30 system clock frequency (mhz) i dd dd i dd (ma) (ma) (ma) default cpu efficiency low-current
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 64 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 11.3 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code accessing the periphe ral is executed. measured on a typical sample at t amb =25 ? c. unless noted otherwise, th e system oscillator and pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 72 mhz. table 12. power consumption for indi vidual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 72 mhz irc 0.008 - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.220 - - irc runn ing; pll off; independent of main clock frequency. watchdog oscillator 0.002 - - system o scillator running; pll off; independent of main clock frequency. bod 0.045 - - independent of main clock frequency. main pll - 0.085 - - usb pll 0.100 sct pll 0.110 clkout - 0.005 0.01 main clock divided by 4 in the clkoutdiv register. rom - 0.015 0.02 - gpio + pin interrupt/pattern match - 0.55 0.60 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. swm - 0.04 0.29 - input mux 0.05 0.30 iocon - 0.06 0.40 - sctimer0/pwm - 0.18 1.10 - sctimer1/pwm - 0.19 1.10 - sctimer2/pwm - 0.13 0.70 - sctimer3/pwm - 0.16 0.90 - sct ipu 0.02 0.1 rtc - 0.01 0.05 - mrt - 0.03 0.10 - wwdt - 0.01 0.10 main clock select ed as clock source for the wdt. rit 0.07 0.20 qei 0.12 0.80 i2c0 - 0.02 0.12 - spi0 - 0.03 0.3 - spi1 - 0.01 0.28 -
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 65 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 11.4 electrical pin characteristics usart0 - 0.02 0.15 - usart1 - 0.02 0.16 - usart2 - 0.02 0.15 - c_can - 0.50 3.00 usb - 0.10 0.50 comparator acmp0/1/2/3 - 0.01 0.03 - adc0 - 0.05 0.33 - adc1 - 0.04 0.33 - temperature sensor - 0.03 0.03 internal voltage reference/band gap - 0.03 0.04 dac - 0.02 0.09 - dma - 0.36 1.5 crc - 0.01 0.08 - table 12. power consumption for indi vidual analog and digital blocks ?continued peripheral typical supply current in ma notes n/a 12 mhz 72 mhz conditions: v dd = 3.3 v; on pin pio0_24. fig 27. high-drive output: typical high-level output voltage v oh versus high-level output current i oh aaa-011257 0 10 20 30 40 50 2.7 2.8 2.9 3 3.1 3.2 3.3 i oh (ma) v oh oh v oh (v) (v) (v) -40 c 25 c 90 c 105 c
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 66 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; on pins pio0_22 and pio0_23. fig 28. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol conditions: v dd = 3.3 v; standard port pins and high-drive pin pio0_24. fig 29. typical low-l evel output current i ol versus low-level output voltage v ol aaa-011258 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 v ol (v) i oh oh i ol (ma) (ma) (ma) -40 c 25 c 90 c 105 c aaa-011263 0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 i ol (ma) v ol ol v ol (v) (v) (v) -40 c 25 c 90 c 105 c
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 67 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 30. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd = 3.3 v; standard port pins. fig 31. typical pull-up current i pu versus input voltage v i aaa-011276 0 3 6 9 12 2.7 2.9 3.1 3.3 v oh (v) i oh oh i oh (ma) (ma) (ma) -40 c 25 c 90 c 105 c aaa-011277 0 1 2 3 4 5 -80 -60 -40 -20 0 v i (v) i pd pd i pu (a) (a) (a) 105 c 90 c 25 c -40 c
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 68 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 32. typical pull-down current i pd versus input voltage v i aaa-011278 0 1 2 3 4 5 0 20 40 60 80 v i (v) i pu pu i pu (a) (a) (a) -40 c 25 c 90 c 105 c
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 69 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 12. dynamic characteristics 12.1 flash/eeprom memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes to the flash. t amb <= +85 ? c. flash programming with iap calls (see lpc15xx user manual ). 12.2 external clock for th e oscillator in slave mode remark: the input voltage on the xtalin and xtalout pins must be ? 1.95 v (see ta b l e 11 ). for connecting the oscillator to the xtal pins, also see section 14.2 . [1] parameters are valid over operating temp erature range unless otherwise specified. table 13. flash characteristics t amb = ? 40 ? c to +105 ? c. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 20 - years not powered 20 40 - years t er erase time page or multiple consecutive pages, sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 14. eeprom characteristics t amb = ? 40 ? cto+85 ? c; v dd = 2.7 v to 3.6 v. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance 100000 1000000 - cycles t ret retention time powered 100 200 - years not powered 150 300 - years t prog programming time 64 bytes - 2.9 - ms table 15. dynamic characteristic : external clock (xtalin input) t amb = ? 40 ? c to +105 ? c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 70 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [2] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. 12.3 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. fig 33. external clock timing (with an amplitude of at least v i(rms) = 200 mv) w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ w &+&/ w &/&; w &+&; 7 f\fon w &/&+ ddd table 16. dynamic char acteristics: irc t amb = ? 40 ? c to +105 ? c; 2.7 v ? v dd ? 3.6 v [1] . symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency ? 25 ?c ? t amb ? +85 ? c 12 - 1% 12 12 + 1 % mhz ? 40 ?c ? t amb < ? 25 ? c 12 - 2% 12 12 + 1 % mhz 85 ?c < t amb ? 105 ? c 12 - 1.5 % 12 12 + 1.5 % mhz conditions: frequency values are typical values. 12 mhz ? 1 % accuracy is guaranteed for 2.7 v ? v dd ? 3.6 v and t amb = ?25 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 34. typical internal rc oscillator frequency versus temperature aaa-011233 -40 -10 20 50 80 110 11.85 11.9 11.95 12 12.05 12.1 12.15 temperature (c) f osc(rc) osc(rc) f osc(rc) (mhz) (mhz) (mhz) 3.6 v 3.3 v 3.0 v 2.7 v
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 71 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +105 ? c) is ? 40 %. 12.4 i/o pins [1] applies to standard port pins and reset pin. 12.5 i 2 c-bus table 17. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency - [2] -503-khz table 18. dynamic characteristics: i/o pins [1] t amb = ? 40 ? c to +105 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 19. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c; values guaranteed by design. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus; on pins pio0_22 and pio0_23 01mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus; on pins pio0_22 and pio0_23 - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus; on pins pio0_22 and pio0_23 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus; on pins pio0_22 and pio0_23 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus; on pins pio0_22 and pio0_23 0- ? s
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 72 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with res pect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low per iod of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus; on pins pio0_22 and pio0_23 50 - ns table 19. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c; values guaranteed by design. [2] symbol parameter conditions min max unit fig 35. i 2 c-bus pins clock timing ddd w i 6'$ w i 6 w +''$7 6&/ i 6&/ w 9''$7 w +,*+ w /2: w 68'$7
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 73 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 12.6 spi interfaces the maximum data bit rate is 17 mbit/s in master mode and in slave mode. remark: spi functions can be assigned to all digita l pins. the characteristics are valid for all digital pins except the open-drain pins pio0_22 and pio0_23. table 20. spi dynamic characteristics t amb = ? 40 ? c to 105 ? c; 2.4 v <= v dd <= 3.6 v; c l = 10 pf; input slew = 1 ns. simulated parameters sampled at the 50 % level of the rising or falling edge; values guaranteed by design. symbol parameter min max unit spi master t ds data set-up time 30 - ns t dh data hold time 0 - ns t v(q) data output valid time - 4 ns t h(q) data output hold time 2 - ns spi slave t ds data set-up time 6 - ns t dh data hold time 0 - ns t v(q) data output valid time - 29 ns t h(q) data output hold time 12 - ns t cy(clk) = cclk/divval with cclk = system clock fr equency. divval is the spi clock divider. see the lpc15xx user manual um10736 . fig 36. spi master timing 6&.&32/ 026, 0,62 7 f\fon w '6 w '+ w y4 '$7$9$/,' '$7$9$/,' w k4 6&.&32/ '$7$9$/,' '$7$9$/,' 026, 0,62 w '6 w '+ '$7$9$/,' '$7$9$/,' w k4 '$7$9$/,' '$7$9$/,' w y4 &3+$ &3+$ ddd
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 74 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fig 37. spi slave timing 6&.&32/ 026, 0,62 7 f\fon w '6 w '+ w y4 '$7$9$/,' '$7$9$/,' w k4 6&.&32/ '$7$9$/,' '$7$9$/,' 026, 0,62 w '6 w '+ w y4 '$7$9$/,' '$7$9$/,' w k4 '$7$9$/,' '$7$9$/,' &3+$ &3+$ ddd
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 75 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 12.7 usart interface the maximum usart bit rate is 15 mbit/s in synchronous mode master mode and 18 mbit/s in synchronous slave mode. remark: usart functions can be assigned to all di gital pins. the characteristics are valid for all digital pins except the ope n-drain pins pio0_22 and pio0_23. table 21. usart dynamic characteristics t amb = ? 40 ? c to 105 ? c; 2.4 v <= v dd <= 3.6 v; c l = 10 pf; input slew = 10 ns. simulated parameters sampled at the 50 % level of the fall ing or rising edge; values guaranteed by design. symbol parameter min max unit usart master (in synchronous mode) t su(d) data input set-up time 33 - ns t h(d) data input hold time 0 - ns t v(q) data output valid time - 7 ns t h(q) data output hold time 2 - ns usart slave (in synchronous mode) t su(d) data input set-up time 13 - ns t h(d) data input hold time 0 - ns t v(q) data output valid time - 28 ns t h(q) data output hold time 12 - ns in master mode, t cy(clk) = u_pclk/brgval. see the lpc15xx user manual um10736 . fig 38. usart timing 8qb6&/.&/.32/ 7;' 5;' 7 f\fon w vx' w k' w y4 67$57 %,7 w k4 8qb6&/.&/.32/ 67$57 %,7 %,7 %,7 ddd
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 76 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 12.8 sct output timing 13. characteristics of analog peripherals [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see the lpc15xx user manual . table 22. sct output dynamic characteristics t amb = ? 40 ? c to 105 ? c; 2.4 v <= v dd <= 3.6 v c l = 10 pf. simulated skew (over process, voltage, and temperature) of any two sct fi xed-pin output signals; sampled at the 50 % level of the falling or rising edge; values guaranteed by design. symbol parameter conditions min typ max unit t sk(o) output skew time sctimer0/pwm - - 4 ns sctimer1/pwm - - 3 ns sctimer2/pwm - - 1 ns sctimer3/pwm - - 2 ns table 23. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 2 assertion - 2.55 - v de-assertion - 2.69 - v interrupt level 3 assertion - 2.83 - v de-assertion - 2.96 - v reset level 2 assertion - 2.34 - v de-assertion - 2.49 - v reset level 3 assertion - 2.64 - v de-assertion - 2.79 - v
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 77 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] the input resistance of adc channel 0 is higher than for all other channels. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 40 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 40 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 40 . [5] the full-scale error voltage or gain error (e g ) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the stra ight line which fits the ideal transfer curve. see figure 40 . [6] t amb = 25 ? c; maximum sampling frequency f s = 2 msamples/s and analog input capacitance c ia = 0.1 pf. [7] input impedance z i is inversely proportional to the sampling frequency and the total input capacity including c ia and c io : z i ? 1 / (f s ? c i ). see table 11 for c io . table 24. 12-bit adc stat ic characteristics t amb = ? 40 ? c to +105 ? c; v dd = 2.4 v to 3.6 v; vrefp = v dda ; v ssa = 0; vrefn = v ssa . symbol parameter conditions min max unit v ia analog input voltage [1] 0v dda v c ia analog input capacitance -0.32pf f clk(adc) adc clock frequency v dda ??? 2.7 v 50 mhz v dda ??? 2.4 v 25 mhz f s sampling frequency v dda ??? 2.7 v - 2 msamples/s v dda ??? 2.4 v - 1 msamples/s e d differential linearity error [2] -+/- 2lsb e l(adj) integral non-linearity [3] -+/- 2lsb e o offset error [4] -+/- 3lsb v err(fs) full-scale error voltage 2 msamples/s [5] - +/- 0.12 % 1 msamples/s +/- 0.07 % z i input impedance f s = 2 msamples/s [6][7] 0.1 - m ? fig 39. adc input impedance dac adc r sw = 5 ...25 r 1 = 0.25 k...2.5 k c ia c dac adcn_0 adcn_[1:11] aaa-011748 c io c io
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 78 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 40. 12-bit adc characteristics 002aaf436 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp - v ss 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 79 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 25. dac static and dy namic characteristics v dda = 2.4 v to 3.6 v; t amb = ? 40 ? c to +105 ? c unless otherwise specified; c l = 100 pf; r l =10k ? .. symbol parameter conditions min typ [1] max unit f c(dac) dac conversion frequency - - 500 ksamples/s r o output resistance - 300 ? t s settling time - - 2.5 ? s e d differential linearity error -- +/-0.4 lsb e l(adj) integral non-linearity -- +/-3 lsb e o offset error vdda = 3.3 v - - +/-9 lsb vdda = 2.4 v - - +/-8 lsb e g gain error - - +/- 0.1 % v o output voltage output voltage range with less than 1 lsb deviation; with minimum r l connected to ground or power supply -- v dda - 0.3 v fig 41. dac test circuit dac 10 k dvm lpcxxxx r l aaa-011964
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 80 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] maximum and minimum values are measured on samples from the corners of the process matrix lot. [2] settling time applies to switching between comparator and adc channels. table 26. internal voltage reference static and dynamic characteristics symbol parameter conditions min typ max unit v o output voltage t amb = ? 40 ? c to +105 ?c [1] 875 - 925 mv t amb = 25 ?c 905 mv t s(pu) power-up settling time to 99% of v o - - 125 ? s v dda = 3.3 v; averaged over process corners fig 42. average internal voltage reference output voltage aaa-011179 -40 -10 20 50 80 110 890 895 900 905 910 915 920 temperature (c) voltage voltage voltage (v) (v) (v)
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 81 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] absolute temperature accuracy. [2] typical values are deriv ed from nominal simulation (v dda = 3.3 v; t amb = 27 ? c; nominal process models). maximum values are derived from worst case simulation (v dda = 2.6 v; t amb = 105 ? c; slow process models). [3] internal voltage reference must be powered before the temperature sensor can be turned on. [4] settling time applies to switching between comparator and adc channels. [1] measured over matrix samples. [2] measured for samples over process corners. table 27. temperature sensor stati c and dynamic characteristics v dda = 2.4 v to 3.6 v symbol parameter conditions min typ max unit dt sen sensor temperature accuracy t amb = ? 40 ? c to +105 ?c [1] -- 5 ?c e l linearity error t amb = ? 40 ? c to +105 ? c- - 5 ?c t s(pu) power-up settling time to 99% of temperature sensor output value [2] [3] -81 110 ? s table 28. temperature sensor linear-least-square (lls) fit parameters v dda = 2.4 v to 3.6 v fit parameter range min typ max unit lls slope t amb = ? 40 ? c to +105 ?c [1] - -2.29 - mv/ ?c lls intercept at 0 ?ct amb = ? 40 ? c to +105 ?c [1] - 577.3 - mv value at 30 ?c [2] 502 - 514 mv v dda = 3.3 v; measured on matrix samples. fig 43. lls fit of the temperature sensor output voltage aaa-011334 -40 -10 20 50 80 110 0 200 400 600 800 temperature (c) v o v o (mv) (mv) (mv) measured temperature sensor output measured temperature sensor output measured temperature sensor output lls fit lls fit lls fit
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 82 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] c l = 10 pf; results from measurements on silicon samples ov er process corners and over the full temperature range t amb = -40 ? c to +105 ? c. [2] input hysteresis is relative to the referenc e input channel and is software programmable. table 29. comparator characteristics v dda = 3.0 v. dly = 0x0 in the analog comparator ctrl register for shortest propagation delay setting. see the lpc15xx user manual um10736. symbol parameter conditions min typ max unit static characteristics i dd supply current vp > vm - 48 - ? a vm > vp - 38 - ? a v ic common-mode input voltage 0 - v dda v dv o output voltage variation 0 - v dd v v offset offset voltage v ic = 0.1 v - +/- 3 - mv v ic = 1.5 v - +/- 3 - mv v ic = 2.9 v - +/- 6 - mv dynamic characteristics t startup start-up time nominal process - 4.5 6 ? s t pd propagation delay high to low; v dda = 3.0 v; v ic = 0.1 v; 50 mv overdrive input [1] - 86 130 ns v ic = 0.1 v; rail-to-rail input [1] - 196 250 ns v ic = 1.5 v; 50 mv overdrive input [1] - 68 110 ns v ic = 1.5 v; rail-to-rail input [1] -64 90 ns v ic = 2.9 v; 50 mv overdrive input [1] - 86 130 ns v ic = 2.9 v; rail-to-rail input [1] -48 80 ns t pd propagation delay low to high; v dda = 3.0 v; v ic = 0.1 v; 50 mv overdrive input [1] - 98 130 ns v ic = 0.1 v; rail-to-rail input [1] -24 40 ns v ic = 1.5 v; 50 mv overdrive input [1] - 88 130 ns v ic = 1.5 v; rail-to-rail input [1] - 68 120 ns v ic = 2.9 v; 50 mv overdrive input [1] - 84 110 ns v ic = 2.9 v; rail-to-rail input [1] - 98 180 ns v hys hysteresis voltage positive hysteresis; v dda = 3.0 v; v ic = 1.5 v; settings: 5 mv [2] 3- 8 mv 10 mv 8 - 13 mv 15 mv 17 - 25 mv v hys hysteresis voltage negative hysteresis; v dda = 3.0 v; v ic = 1.5 v; settings: 5 mv [1][2] 3- 9 mv 10 mv 8 - 18 mv 15 mv 18 - 27 mv r lad ladder resistance - - 1 - m ?
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 83 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller [1] measured over a polyresistor matrix lot with a 2 khz input signal and overdrive < 100 ? v. [2] all peripherals except comparator, temperature sensor, and irc turned off. table 30. comparator voltage ladder dynamic characteristics symbol parameter conditions min typ max unit t s(pu) power-up settling time to 99% of voltage ladder output value --30 ? s t s(sw) switching settling time to 99% of voltage ladder output value --20 ? s table 31. comparator voltage ladder reference static characteristics v dd(3v3) = 3.3 v; t amb = -40 ? c to + 105 ? c; external or internal reference. symbol parameter conditions min typ max [1] unit e v(o) output voltage error decimal code = 00 [2] -03 mv decimal code = 08 -1.5 0 +1.5 % decimal code = 16 -1.5 0 +1.5 % decimal code = 24 -1.5 0 +1.5 % decimal code = 30 -1.5 0 +1.5 % decimal code = 31 -1.5 0 +1.5 %
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 84 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 14. application information 14.1 suggested usb interface solutions the usb device can be connected to the usb as self-powered device (see figure 44 ) or bus-powered device (see figure 45 ). on the lpc15xx, the pio0_3/usb_vbus pin is 5 v tolerant only when v dd is applied and at operating voltage level. therefore, if the usb_vbus function is connected to the usb connector and the device is self-powered , the usb_vbus pin must be protected for situations when v dd = 0 v. if v dd is always greater than 0 v while vbus = 5 v, the usb_vbus pin can be connected directly to the vbus pin on the usb connector. for systems where v dd can be 0 v and vbus is directly applied to the vbus pin, precautions must be taken to reduce the voltage to below 3.6 v, which is the maximum allowable voltage on the usb_vbus pin in this case. one method is to use a voltage divider to connect the usb_vbus pin to the vbus on the usb connector. the voltage divider ratio shou ld be such that the usb_vbus pin will be greater than 0.7v dd to indicate a logic high while below the 3.6 v allowable maximum voltage. for the following operating conditions vbus max = 5.25 v v dd = 3.6 v, the voltage divider should provide a reduction of 3.6 v/5.25 v or ~0.686 v. for a bus-powered device, the vbus signal does not need to be connected to the usb_vbus pin (see figure 45 ). the usb_connect function can additionally be enabled internally by setting the dcon bit in the devcmdstat register to prevent the usb from timing out when there is a significant delay between power-up and handling usb traffic. external circuitry is not required for the usb_connect functionality. fig 44. usb interface on a self-powered device where usb_vbus = 5 v lpc1xxx v dd r1 1.5 k aaa-010820 usb-b connector usb_dp usb_dm usb_vbus v ss r s = 33 r s = 33 usb usb_connect r2 r3
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 85 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller remark: when a bus-powered circuit as shown in figure 45 is used or, for a self-powered device, when the vbus pin is not connect ed, configure the pio0_3/usb_vbus pin for gpio (pio0_3) in the iocon block. this ties the vbus signal high internally. 14.1.1 usb low-speed operation the usb device controller can be used in low-speed mode supporting 1.5 mbit/s data exchange with a usb host controller. remark: to operate in low-speed mode, change the board connections as follows: 1. connect usb_dp to the d- pin of the connector. 2. connect usb_dm to the d+ pin of the connector. external 10 ? resistors are recommended in low-speed mode to reduce over-shoots and accommodate for 5 m cable length required for usb-if testing. 14.2 xtal input and crystal osci llator component selection the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. fig 45. usb interface on a bus-powered device regulator vbus lpc1xxx v dd r1 1.5 k aaa-010821 usb-b connector usb_dp usb_dm v ss r s = 33 r s = 33 usb usb_connect
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 86 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 46 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 47 and in ta b l e 3 2 and ta b l e 3 3 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 47 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see ta b l e 3 2 ). fig 46. slave mode operation of the on-chip oscillator fig 47. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 32. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz to 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf lpc1xxx xtalin c i 100 pf c g 002aae788 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 87 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 14.3 xtal printed-circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plane. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as po ssible. smaller values of c x1 and c x2 should be chosen according to the increase in parasitics of the pcb layout. 5 mhz to 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz to 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz to 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 33. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz to 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz to 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf table 32. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 88 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 14.4 rtc oscillator component selection the 32 khz crystal must be connected to the part via the rtcxin and rtcxout pins as shown in figure 48 . if the rtc is not used, the rtcxin pin can be grounded. select c x1 and c x2 based on the external 32 khz crystal used in the application circuitry.the pad capacitance c p of the rtcxin and rtcxout pad is 3 pf. if the external crystal?s load capacitance is c l , the optimal c x1 and c x2 can be selected as: c x1 = c x2 = 2 x c l ? c p fig 48. rtc oscillator components lpc1xxx rtcxin rtcxout c x2 c x1 xtal = c l c p r s l aaa-010822
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 89 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 15. package outline fig 49. package outline lqfp48 (sot313-2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 90 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fig 50. package outline lqfp64 (sot314-2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1)(1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 91 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fig 51. package outline lqfp100 (sot407-1) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1)(1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 92 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 16. soldering fig 52. reflow soldering for the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 93 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fig 53. reflow soldering for the lqfp64 package sot314-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp64 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 94 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller fig 54. reflow soldering for the lqfp100 package sot407-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp100 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot407-1 solder land c generic footprint pattern refer to the package outline drawing for actual layout 17.300 17.300 14.300 14.300 0.500 0.560 0.280 1.500 0.400 14.500 14.500 17.550 17.550
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 95 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 17. references [1] lpc15xx user manual um10736: http://www.nxp.com/documen ts/user_manual/um10736.pdf [2] lpc15xx errata sheet: http://www.nxp.com/documents /errata_sheet/es_lpc15xx.pdf 18. revision history table 34. revision history document id release date data sheet status change notice supersedes lpc15xx v.1 20140219 product data sheet - -
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 96 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 97 of 99 nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc15xx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 19 february 2014 98 of 99 continued >> nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 8 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 12 8 functional description . . . . . . . . . . . . . . . . . . 21 8.1 arm cortex-m3 processor . . . . . . . . . . . . . . . 21 8.2 memory protection unit (mpu). . . . . . . . . . . . 21 8.3 on-chip flash programming memory . . . . . . . 22 8.3.1 isp pin configuration . . . . . . . . . . . . . . . . . . . 22 8.4 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.5 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.6 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7 ahb multilayer matrix . . . . . . . . . . . . . . . . . . . 24 8.8 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.9 nested vectored interrupt controller (nvic) . . 26 8.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.9.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 26 8.10 iocon block . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.10.2 standard i/o pad configuration . . . . . . . . . . . . 26 8.11 switch matrix (swm) . . . . . . . . . . . . . . . . . . . 27 8.12 fast general-purpose parallel i/o (gpio) . . . 28 8.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.13 pin interrupt/pattern match engine (pint) . . . 28 8.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.14 gpio group interrupts (gint0/1) . . . . . . . . . . 29 8.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.16 input multiplexing (input mux) . . . . . . . . . . . . 30 8.17 usb interface . . . . . . . . . . . . . . . . . . . . . . . . 30 8.17.1 full-speed usb device controller . . . . . . . . . . 30 8.17.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.18 usart0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19 spi0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.20 i2c-bus interface . . . . . . . . . . . . . . . . . . . . . . 32 8.20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21 c_can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.22 pwm/timer/motor control subsystem . . . . . . . 33 8.22.1 sctimer/pwm s ubsystem . . . . . . . . . . . . . . . 33 8.22.2 timer controlled subsyste m . . . . . . . . . . . . . . 34 8.22.3 sctimer/pwm in the large configuration (sct0/1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.22.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.22.4 state-configurable timers in the small configuration (sct2/3). . . . . . . . . . . . . . . . . . 37 8.22.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.22.5 sct input processing unit (sctipu) . . . . . . . 38 8.22.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.23 quadrature encoder inte rface (qei) . . . . . . . 39 8.23.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.24 analog-to-digital converter (adc). . . . . . . . . 39 8.24.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.25 digital-to-analog converter (dac). . . . . . . . . 40 8.25.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.26 analog comparator (acmp) . . . . . . . . . . . . . . 40 8.26.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.27 temperature sensor . . . . . . . . . . . . . . . . . . . . 41 8.28 internal voltage reference . . . . . . . . . . . . . . . 41 8.29 multi-rate timer (mrt) . . . . . . . . . . . . . . . . . 42 8.29.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30 windowed watchdog ti mer (wwdt) . . . . . . 42 8.30.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.31 repetitive interrupt (ri) timer. . . . . . . . . . . . . 43 8.31.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.32 system tick timer . . . . . . . . . . . . . . . . . . . . . . 43 8.33 real-time clock (rtc) . . . . . . . . . . . . . . . . . 43 8.33.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.34 clock generation . . . . . . . . . . . . . . . . . . . . . . 44 8.35 power domains . . . . . . . . . . . . . . . . . . . . . . . 45 8.36 integrated oscillators . . . . . . . . . . . . . . . . . . . 45 8.36.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 46 8.36.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 46 8.36.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 46 8.36.4 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 46 8.37 system pll, usb pll, and sct pll . . . . . . 46 8.38 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.39 wake-up process . . . . . . . . . . . . . . . . . . . . . . 47 8.40 power control . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.40.1 power profiles . . . . . . . . . . . . . . . . . . . . . . . . 47 8.40.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.40.3 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 48 8.40.4 power-down mode . . . . . . . . . . . . . . . . . . . . . 48 8.40.5 deep power-down mode . . . . . . . . . . . . . . . . 48 8.41 system control . . . . . . . . . . . . . . . . . . . . . . . . 49
nxp semiconductors lpc15xx 32-bit arm cortex-m3 microcontroller ? nxp b.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 19 february 2014 document identifier: lpc15xx please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 8.41.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.41.2 brownout detection . . . . . . . . . . . . . . . . . . . . . 49 8.41.3 code security (code read protection - crp) 49 8.42 emulation and debugging . . . . . . . . . . . . . . . . 51 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 51 10 thermal characteristics . . . . . . . . . . . . . . . . . 52 11 static characteristics. . . . . . . . . . . . . . . . . . . . 54 11.1 power consumption . . . . . . . . . . . . . . . . . . . . 59 11.2 coremark data . . . . . . . . . . . . . . . . . . . . . . . . 63 11.3 peripheral power consumpt ion . . . . . . . . . . . . 64 11.4 electrical pin characteristics . . . . . . . . . . . . . . 65 12 dynamic characteristics . . . . . . . . . . . . . . . . . 69 12.1 flash/eeprom memory . . . . . . . . . . . . . . . . 69 12.2 external clock for the oscillator in slave mode 69 12.3 internal oscillators. . . . . . . . . . . . . . . . . . . . . . 70 12.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.6 spi interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.7 usart interface. . . . . . . . . . . . . . . . . . . . . . . 75 12.8 sct output timing . . . . . . . . . . . . . . . . . . . . . . 76 13 characteristics of analog peripherals . . . . . . 76 14 application information. . . . . . . . . . . . . . . . . . 84 14.1 suggested usb interface solutions . . . . . . . . 84 14.1.1 usb low-speed operation . . . . . . . . . . . . . . . 85 14.2 xtal input and crystal oscillator component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.3 xtal printed-circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.4 rtc oscillator component selection . . . . . . . . 88 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 89 16 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 17 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . 95 19 legal information. . . . . . . . . . . . . . . . . . . . . . . 96 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 96 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 19.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 97 20 contact information. . . . . . . . . . . . . . . . . . . . . 97 21 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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